RFID tags with power rectifiers that have bias

• US 7,561,866 B2
• Filed: 09/26/2005
• Issued: 07/14/2009
• Est. Priority Date: 02/22/2005
• Status: Active Grant

• Current Assignee: Impinj, Inc.
• Original Assignee: Impinj, Inc.
• Inventors: Oliver, Ronald A., Diorio, Christopher J.
• Primary Examiner(s): Le; Nhan T
• Application Number:
  US11/236,709
• Publication Number:
  US 20060197668A1
• Time in Patent Office: 1,387 Days
• Field of Search: 455/127.1, 455/127.5, 455/323, 455/333, 4553431-3433, 327/534, 327/535, 340/635, 340/645, 363/59, 363/60, 363/61
• US Class Current: 455/343.3
• CPC Class Codes: G06K 19/0701 at least one of the integrated circuit chips comprising an arrangement for power management
• CPC Class Codes: G06K 19/0723 the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs

Abstract

A system and method for generating a rectified signal in a RFID tag. An alternating signal is received by the RFID tag, and a first phase of the alternating signal is coupled to a gate and to a first non-controlling terminal of a first switching transistor. The non-controlling terminal of the first switching transistor is one of a source and a drain of the first switching transistor. A first bias voltage is applied between the first non-controlling terminal and the first gate of the first switching transistor and a rectified voltage is received between the first non-controlling terminal and a second non-controlling terminal of the first switching transistor.

Claims

1. An RFID circuit comprising:

first and second input nodes to render an alternating signal between them; and

a power management unit having a plurality of successive stages, each stage having first and second control nodes coupled to the first and second input nodes respectively, a first one of the stages including;

a first switching transistor having a gate and first and second non-controlling terminals, the non-controlling terminals of the first switching transistor being a source and a drain, the gate and the first non-controlling terminal being coupled to receive a first phase of the alternating signal from the first control node of the first stage, and

wherein an additional first bias voltage is adapted to be applied between the first non-controlling terminal and the gate of the first switching transistor, and

wherein a rectified voltage is adapted to be received between the first and the second non-controlling terminals.

2. The RFID circuit of claim 1, further comprising:

first and second antenna pads coupled respectively to the first and second input nodes, the first and second antenna pads adapted to be coupled to REID antenna segments.

3. The RFID circuit of claim 1, further comprising:

an oscillator coupled to output to the input nodes two phases that present the alternating signal in relation to each other.

4. The RFID circuit of claim 1, wherein the stages are identical.

5. The RFID circuit of claim 1, wherein the bias voltage is adjustable.

6. The RFID circuit of claim 1, wherein the first stage further includes a first capacitor coupled between the first control node and the gate and the first non-controlling terminal of the first switching transistor.

7. The RFID circuit of claim 1, wherein the first stage further includes a first capacitor coupled between the first control node and the gate of the first switching transistor;

and

a second capacitor coupled between the first control node and the first non-controlling terminal of the first switching transistor.

8. The RFID circuit of claim 1, wherein the first stage further includes a bias circuit adapted to provide the bias voltage.

9. The RFID circuit of claim 8, wherein the bias circuit includes a reference transistor having a first terminal coupled to the gate of the first switching transistor and a second terminal coupled to the first non-controlling terminal of the first transistor.

10. The RFID circuit of claim 9, wherein the first terminal of the reference transistor is a gate of the reference transistor.

11. The RFID circuit of claim 9, wherein the reference transistor also has a third terminal that is shorted to one of the first terminals and the second terminals.

12. The RFID circuit of claim 9, wherein the reference transistor also has a third terminal that is adapted to receive a bias current.

13. The RFID circuit of claim 12, wherein the bias current is adapted to be in phase with the first phase of the alternating current.

14. The RFID circuit of claim 12, wherein the bias circuit further includes a current source for applying the bias current.

15. The RFID circuit of claim 14, wherein the first terminal of the reference transistor is a gate and a floating gate is formed with the gate of the first switching transistor, the current source providing a tunneling current to the reference transistor.

16. The RFID circuit of claim 14, wherein the third terminal and first terminals of the reference transistor are coupled.

17. The RFID circuit of claim 16, wherein the first terminal of the reference transistor is coupled to the gate of the first switching transistor through a switch.

18. The RFID circuit of claim 14, wherein the current source is an adjustable current source for applying an adjustable bias current.

19. The RFID circuit of claim 18, wherein the bias circuit further includes an envelope detector for determining an amplitude of the alternating signal and generating a control signal to adjust the current source based on the amplitude.

20. The RFID circuit of claim 18, wherein the bias circuit further includes a voltage sensing circuit coupled to the first switching transistor, the voltage sensing circuit for generating a control signal to adjust the current source based on a voltage across the first switching transistor.

21. The RFID circuit of claim 18, wherein the bias circuit further includes a current sensing circuit coupled to the first switching transistor, the current sensing circuit for generating a control signal to adjust the current source based on a current of the first switching transistor.

22. The RFID circuit of claim 1, wherein the first stage further includes a second switching transistor having a gate and a first non-controlling terminal coupled to receive a second phase of the alternating signal from the second control node of the first stage, the non-controlling terminal of the second switching transistor being one of a source and a drain of the second switching transistor, and

wherein the first non-controlling terminal of the second switching transistor is coupled with the second non-controlling terminal of the first switching transistor,

an additional second bias voltage is adapted to be applied between the first non-controlling terminal and the gate of the second switching transistor, and

wherein the rectified voltage is adapted to be received between the first non-controlling terminal of the first switching transistor and the second non-controlling terminal of the second switching transistor.

23. The RFID circuit of claim 22, wherein the first switching transistor comprises a n-channel field effect transistor and the second switching transistor comprises a n-channel field effect transistor, and the RFID circuit further comprises:

a first bias circuit adapted to provide the first bias voltage; and

a second bias circuit adapted to provide the second bias voltage.

24. The RFID circuit of claim 1, wherein the first stage further includes a second switching transistor having a gate, the second switching transistor also having a first non-controlling terminal coupled to receive a second phase of the alternating signal from the second control node of the first stage, the non-controlling terminal of the second switching transistor being one of a source and a drain of the second switching transistor, and

wherein the first non-controlling terminal of the second switching transistor is coupled with the second non-controlling terminal of the first switching transistor,

an additional second bias voltage is adapted to be applied between the second non-controlling terminal and the gate of the second switching transistor, and

wherein the rectified voltage is adapted to be received between the first non-controlling terminal of the first switching transistor and the second non-controlling terminal of the second switching transistor.

25. The RFID circuit of claim 24, wherein the first switching transistor comprises a n-channel field effect transistor and the second switching transistor comprises a p-channel field effect transistor, and the RFID circuit further comprises:

a first bias circuit adapted to provide the first bias voltage; and

a second bias circuit adapted to provide the second bias voltage.

26. The RFJD circuit of claim 25, wherein the first bias circuit includes a first reference transistor having a first terminal coupled to the gate of the n-channel field effect transistor and a second terminal coupled to the first non-controlling terminal of the first transistor and wherein the second bias circuit includes a second reference transistor having a terminal coupled to the gate of the p-channel field effect transistor and a second terminal coupled to the second non-controlling terminal of the second transistor.

27. The RFID circuit of claim 26, wherein the first and second reference transistors have third terminals adapted to receive a respective bias current.

28. The RFJD circuit of claim 27, wherein the bias current received by the third terminal of the first reference transistor is provided by a first current source and the bias current received by the third terminal of the second reference transistor is provided by a second current source.

29. The RFID circuit of claim 28, wherein the first and second current sources are the same current source.

30. The RFID circuit of claim 28, wherein the first and second current sources are adjustable to provide respective adjustable bias currents.