Method for using data regarding manufacturing procedures integrated circuits (ICS) have undergone, such as repairs, to select procedures the ICs will undergo, such as additional repairs

• US 7,561,938 B2
• Filed: 10/06/2006
• Issued: 07/14/2009
• Est. Priority Date: 06/06/1997
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Hess, Michael E., Jacobson, John O., Gochnour, Derek J., Farnworth, Warren M., Hembree, David R., Wark, James M., Wood, Alan G., Akram, Salman
• Primary Examiner(s): DeCady; Albert
• Assistant Examiner(s): Garland; Steven R
• Application Number:
  US11/545,067
• Publication Number:
  US 20070088451A1
• Time in Patent Office: 1,012 Days
• Field of Search: 700/109, 700/121, 700/116, 700/118, 702/117, 702/118
• US Class Current: 700/121
• CPC Class Codes: G03F 7/7065 Defects, e.g. optical inspection of patterned layer for defects
• CPC Class Codes: G06F 11/00 Error detection; Error correction; Monitoring error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00
• CPC Class Codes: G06F 11/006 Identification G06F11/2289 takes precedence
• CPC Class Codes: G16Z 99/00 Subject matter not provided for in other main groups of this subclass
• CPC Class Codes: H01L 2223/5444 for electrical read out

Abstract

An inventive method in an integrated circuit (IC) manufacturing process for using data regarding repair procedures conducted on ICs at probe to determine whether any further repairs will be conducted later in the manufacturing process includes storing the data in association with a fuse ID of each of the ICs. The ID codes of the ICs are automatically read, for example, at an opens/shorts test during the manufacturing process. The data stored in association with the ID codes of the ICs is then accessed, and additional repair procedures the ICs may undergo are selected in accordance with the accessed data. Thus, for example, the accessed data may indicate that an IC is unrepairable, so the IC can proceed directly to a scrap bin without having to be queried to determine whether it is repairable, as is necessary in traditional IC manufacturing processes.

Claims

1. An integrated circuit manufacturing process using data related to manufacturing procedures used previously that a plurality of integrated circuits of Dynamic Random Access Memory (DRAM) semiconductor devices have undergone for selecting manufacturing procedures the plurality of integrated circuits of the Dynamic Random Access Memory (DRAM) semiconductor devices are to undergo, each Dynamic Random Access Memory (DRAM) semiconductor device having integrated circuits and having a substantially unique identification code, the manufacturing process comprising:

storing data in association with the substantially unique identification code of each Dynamic Random Access Memory (DRAM) semiconductor device of the plurality identifying manufacturing procedures each Dynamic Random Access Memory (DRAM) semiconductor device has undergone, the storing data comprising storing data that identifies spare rows and columns used in repairing each DRAM semiconductor device;

automatically reading the substantially unique identification code of each Dynamic Random Access Memory (DRAM) semiconductor device;

accessing the data stored in association with the substantially unique identification code of each Dynamic Random Access Memory (DRAM) semiconductor device; and

analyzing the data stored in association with the substantially unique identification code of each Dynamic Random Access Memory (DRAM) semiconductor device for determining the manufacturing procedures used previously for each Dynamic Random Access Memory (DRAM) semiconductor device.

2. The integrated circuit manufacturing process of claim 1, further comprising:

selecting manufacturing procedures each semiconductor device undergoes in accordance with the accessed data.

3. The integrated circuit manufacturing process of claim 2, wherein selecting the manufacturing procedures each semiconductor device undergoes in accordance with the accessed data comprises selecting repairs each semiconductor device undergoes in accordance with the accessed data.

4. The integrated circuit manufacturing process of claim 3, wherein each semiconductor device comprises a Dynamic Random Access Memory (DRAM) semiconductor device, and wherein selecting repairs each semiconductor device undergoes comprises selecting spare rows and columns used to repair each DRAM semiconductor device.

5. The integrated circuit manufacturing process of claim 2, wherein selecting manufacturing procedures each semiconductor device undergoes in accordance with the accessed data comprises selecting whether each semiconductor device undergoes repair procedures.

6. The integrated circuit manufacturing process of claim 5, wherein each semiconductor device comprises a Dynamic Random Access Memory (DRAM) semiconductor device, and wherein selecting whether each semiconductor device undergoes repair procedures comprises selecting whether each DRAM semiconductor device will be repaired in accordance with whether the accessed data indicates enough spare rows and columns are available in each semiconductor device to effect repairs.

7. The integrated circuit manufacturing process of claim 2, wherein selecting manufacturing procedures each semiconductor device will undergo in accordance with the accessed data comprises determining whether each semiconductor device will be assembled into Multi-Chip Modules (MCMs) in accordance with whether the accessed data indicates each semiconductor device is repairable.

8. The integrated circuit manufacturing process of claim 1, wherein storing data comprises storing data that identifies repairs performed on each semiconductor device.

9. The integrated circuit manufacturing process of claim 1, wherein storing data comprises storing data at probe.

10. The integrated circuit manufacturing process of claim 1, wherein automatically reading the substantially unique identification code of each semiconductor device comprises electrically retrieving a unique fuse ID programmed into each semiconductor device.

11. The integrated circuit manufacturing process of claim 1, wherein automatically reading the substantially unique identification code of each semiconductor device comprises optically reading a unique ID code provided on each semiconductor device.

12. The integrated circuit manufacturing process of claim 11, wherein optically reading a unique ID code provided on each semiconductor device comprises optically reading a unique laser fuse ID programmed into each semiconductor device.

13. The integrated circuit manufacturing process of claim 1, wherein automatically reading the substantially unique identification code of each semiconductor device comprises automatically reading the substantially unique identification code of each semiconductor device at one of an opens/shorts test, a burn-in test, and a back-end test in the integrated circuit manufacturing process.

14. The integrated circuit manufacturing process of claim 1, wherein accessing the data stored in association with the substantially unique identification code of each semiconductor device comprises accessing the data stored in association with the substantially unique identification code of each semiconductor device at one of an opens/shorts test, a burn-in test, and a back-end test in the integrated circuit manufacturing process.

15. The integrated circuit manufacturing process of claim 1, further comprising assembling each semiconductor device into a packaged semiconductor device after storing data and before automatically reading the substantially unique identification code of each semiconductor device.

16. A method of manufacturing integrated circuit Dynamic Random Access Memory (DRAM) semiconductor devices from semiconductor wafers, the method comprising:

providing a plurality of semiconductor wafers;

fabricating a plurality of integrated circuit Dynamic Random Access Memory (DRAM) semiconductor devices on each of the semiconductor wafers of the plurality of semiconductor wafers;

causing each integrated circuit Dynamic Random Access Memory (DRAM) semiconductor device of the plurality on each of the semiconductor wafers of the plurality of semiconductor wafers to store a substantially unique identification code;

storing data in association with the substantially unique identification code of each integrated circuit Dynamic Random Access Memory (DRAM) semiconductor device of the plurality that identifies manufacturing procedures each integrated circuit Dynamic Random Access Memory (DRAM) semiconductor device of the plurality has undergone, the storing data comprising storing data that identifies spare rows and columns used in repairing each integrated circuit Dynamic Random Access Memory (DRAM) semiconductor device of the plurality;

separating each integrated circuit Dynamic Random Access Memory (DRAM) semiconductor device of the plurality on each of the semiconductor wafers of the plurality of semiconductor wafers from its wafer to form one integrated circuit Dynamic Random Access Memory (DRAM) semiconductor device of a plurality of integrated circuit Dynamic Random Access Memory (DRAM) semiconductor devices;

assembling each integrated circuit Dynamic Random Access Memory (DRAM) semiconductor device of the plurality into a Dynamic Random Access Memory (DRAM) semiconductor device assembly;

automatically reading the substantially unique identification code associated with each integrated circuit Dynamic Random Access Memory (DRAM) semiconductor device of the plurality;

accessing the data stored in association with the substantially unique identification code associated with each integrated circuit Dynamic Random Access Memory (DRAM) semiconductor device of the plurality; and

reviewing the data stored in association with the substantially unique identification code of each integrated circuit Dynamic Random Access Memory (DRAM) semiconductor device for determining the manufacturing procedures used previously for each integrated circuit Dynamic Random Access Memory (DRAM) semiconductor device.

17. The method of claim 16, further comprising:

selecting manufacturing procedures each semiconductor device undergoes in accordance with the accessed data.

18. The method of claim 16, wherein fabricating a plurality of semiconductor devices on each of the semiconductor wafers of the plurality of semiconductor wafers comprises fabricating semiconductor devices selected from the group comprising Dynamic Random Access Memory (DRAM) semiconductor devices, Static Random Access Memory (SRAM) semiconductor devices, Synchronous DRAM (SDRAM) semiconductor devices, processor semiconductor devices, Rambus in-line memory module type semiconductor devices, small outline Rambus in-line memory module type semiconductor devices, and personal computer memory format type semiconductor devices.

19. The method of claim 16, wherein causing each semiconductor device on each of the semiconductor wafers of the plurality of semiconductor wafers to store a substantially unique identification code comprises programming each semiconductor device on each of the semiconductor wafers of the plurality of semiconductor wafers to permanently store a unique fuse ID.

20. The method of claim 19, wherein programming each semiconductor device on each of the semiconductor wafers of the plurality of semiconductor wafers to permanently store a unique fuse ID comprises programming at least one of fuses and anti-fuses in each semiconductor device on each of the semiconductor wafers of the plurality of semiconductor wafers to permanently store a unique fuse identification.

21. The method of claim 16, wherein assembling each semiconductor device of the plurality of semiconductor devices into a semiconductor device assembly comprises:

picking each semiconductor device of the plurality from its wafer;

placing each semiconductor device of the plurality onto an epoxy-coated bonding site of one lead frame of a plurality of lead frames;

curing the epoxy on the bonding site of each lead frame of the plurality of lead frames;

wire bonding each semiconductor device of the plurality to its associated lead frame;

encapsulating each semiconductor device of the plurality and its associated lead frame to form one of a plurality of semiconductor device assembly packages, each package of the plurality having projecting leads;

curing each of the semiconductor device assembly packages of the plurality;

de-flashing the projecting leads of each semiconductor device assembly package of the plurality;

electroplating the projecting leads of each semiconductor device assembly package of the plurality; and

singulating each semiconductor device assembly package of the plurality into one semiconductor device assembly package of a plurality of discrete semiconductor device assembly packages.

22. The method of claim 16, wherein assembling each semiconductor device of the plurality into a semiconductor device assembly comprises assembling each semiconductor device of the plurality into a semiconductor device assembly selected from the group comprising a wire bond/lead frame semiconductor device, a Chip-On-Board (COB) semiconductor device, a flip-chip semiconductor device, and a Board-Over-Chip (BOC) semiconductor device.

23. A method of manufacturing Multi-Chip Modules (MCMs) from semiconductor wafers, the MCMs selected from the group of Single In-Line Memory Modules (SIMMs) and Dual In-line Memory Modules (DIMMs), Rambus In-Line Memory Modules (RIMMs), Small Outline Rambus In-Line Memory Modules (SO-RIMMs), Personal Computer Memory Card International Association (PCMCIA) format, and Board-Over-Chip type substrates, the method comprising:

providing a plurality of semiconductor wafers;

fabricating a plurality of semiconductor devices on each of the semiconductor wafers of the plurality of semiconductor wafers;

causing each semiconductor device of the plurality of semiconductor devices on each of the semiconductor wafers of the plurality of semiconductor wafers to store a substantially unique identification code;

storing data in association with the substantially unique identification code of each semiconductor device of the plurality of semiconductor devices that identifies manufacturing procedures each semiconductor device of the plurality of semiconductor devices has undergone, the storing data including storing data that identifies rows and columns used in repairing a semiconductor device;

separating each semiconductor device of the plurality of semiconductor devices on each semiconductor wafer of the plurality of semiconductor wafers from its wafer to form one semiconductor device of a plurality of semiconductor devices;

assembling one or more of the semiconductor devices of the plurality into each of a plurality of MCMs;

automatically reading the substantially unique identification code of each semiconductor device of the plurality of semiconductor devices in each MCM of the plurality of MCMs;

accessing the data stored in association with the substantially unique identification code of each semiconductor device of the plurality of semiconductor devices in each MCM of the plurality of MCMs; and

reading the data stored in association with the substantially unique identification code of each semiconductor device of the plurality of semiconductor devices for determining the manufacturing procedures used previously for each semiconductor device of the plurality of semiconductor devices.

24. The method of claim 23, further comprising:

selecting manufacturing procedures each semiconductor device of the plurality of semiconductor devices will undergo in accordance with the accessed data.