Semiconductor device and semiconductor signal processing apparatus

• US 7,562,198 B2
• Filed: 06/09/2005
• Issued: 07/14/2009
• Est. Priority Date: 06/09/2004
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Noda, Hideyuki, Saitoh, Kazunori, Ariomoto, Kazutami, Dosaka, Katsumi
• Primary Examiner(s): Sough; Hyung S
• Assistant Examiner(s): Ahmed; Hamdy S
• Application Number:
  US11/148,369
• Publication Number:
  US 20050285862A1
• Time in Patent Office: 1,496 Days
• Field of Search: 711/145
• US Class Current: 711/154
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

A memory cell mat is divided into a plurality of entries, and an arithmetic logic unit is arranged corresponding to each entry. Between the entries and the corresponding arithmetic logic units, arithmetic/logic operation is executed in bit-serial and entry-parallel manner. Where parallel operation is not very effective, data is transferred in entry-serial and bit-parallel manner to a group of processors provided at a lower portion of the memory mat. In this manner, a large amount of data can be processed at high speed regardless of the contents of operation or data bit width.

Claims

1. A semiconductor device, comprising:

a first processing unit;

an internal bus; and

,

a plurality of operation units each comprising an operational block and an operational control unit,

wherein said first processing unit issues an instruction to the operation units via said internal bus,

wherein each operational block includes a memory array used for storing data and divided into plural entries, and a plurality of first processing elements each of which is arranged corresponding to a respective entry of said memory array and is for performing an arithmetic and logical operation,

wherein each of said plural first processing elements performs an operation instructed by said operational control unit using data provided from first selected memory cells in corresponding entries in parallel and store result of said operation into second selected memory cells in said corresponding entries in parallel, and

wherein said memory array has a first word line selected for activating the first selected memory cells of all the entries, and has a second word line selected for activating said second selected memory cells of all the entries.

2. The semiconductor device according to claim 1, further comprising a connection switching transfer circuit for transferring data among said plurality of first processing elements.

3. The semiconductor device according to claim 1, wherein

each of said plural entries is arranged corresponding to the respective columns of said memory cell array;

and

a data transfer lines for transferring data between the entries and the corresponding first processing elements are arranged corresponding to the respective columns.

4. The semiconductor device according to claim 1, wherein

each of the memory cells is a multi-port memory cell having a write port and a read port, and

said plurality of data transfer lines include a write data line connected to the write ports of the memory cells of the corresponding entry and a read data line connected to the read ports of the memory cells of the corresponding entry.

5. The semiconductor device according to claim 4, further comprising:

a read cell selecting circuit for driving the read ports of memory cells at a same position in the respective entries of said memory cell array to a selected state, and

a write cell selecting circuit, provided separately from and operable in parallel with said read cell selecting circuit, for driving the write ports of memory cells at the same position in the respective entries of said memory cell array to a selected state.

6. The semiconductor device according to claim 1, wherein

said memory cell array is divided into a first memory array and a second memory array so as to divide each of said plurality of entries;

and

said plurality of first processing elements are arranged between the first and second memory arrays, receive data from corresponding entries of said first and second memory arrays, and execute the designated operational processing on received data.

7. The semiconductor device according to claim 1, wherein

each of the first processing elements includes an arithmetic/logic portion for executing an arithmetic or logic operation as the designated operational processing, a register circuit for storing data applied from the corresponding entry, a result register for storing a result of operation of said arithmetic/logic portion, and a mask register for storing mask data for prohibiting the operation by said arithmetic/logic portion.

8. The semiconductor device according to claim 1, wherein

each of the memory cells is a multi-port memory having first and second ports that can be selected independently of each other;

said plurality of memory cells are arranged aligned in a first direction corresponding to one of the row and the column and in a second direction corresponding to another of the row and the column, and

said semiconductor device further comprises;

a plurality of first word lines each arranged corresponding to the memory cells arranged aligned in said first direction and connected to the first ports of corresponding memory cells;

a plurality of first bit lines, each arranged corresponding to the memory cells arranged aligned in said second direction and coupled to the first ports of corresponding memory cells, for forming the data transfer lines;

a plurality of second word lines each arranged corresponding to the memory cells arranged aligned in said second direction and connected to the second ports of corresponding memory cells;

a plurality of second bit lines each arranged corresponding to the memory cells arranged aligned in said first direction and connected to the second ports of corresponding memory cells; and

a plurality of second processing elements arranged facing to and being capable of data transfer with said plurality of second bit lines.

9. The semiconductor device according to claim 8, further comprising

a path changing circuit for changing a data transfer route between said plurality of second bit lines and said plurality of second processing elements.

10. The semiconductor device according to claim 8, wherein

each of the entries stores a multi-bit data word as said multi-bit data, and said plurality of second processing elements performs an arithmetic or logic operation on applied multi-bit data words on a word-by-word basis.

11. The semiconductor device according to claim 8, wherein the second processing elements include processors arranged in a plurality of stages.

12. The semiconductor device according to claim 8, further comprising

an input/output circuit for transferring data between said plurality of second bit lines and an outside of the semiconductor device on an entry-by-entry basis.

13. The semiconductor device according to claim 8, further comprising:

a first shift redundancy repairing circuit arranged corresponding to the first word lines, for repairing a defective address by shifting correspondence between said plurality of first word lines and addresses in accordance with first defective address information;

a second shift redundancy repairing circuit arranged corresponding to the second word lines, for repairing a defective address by shifting correspondence between said plurality of second word lines and addresses in accordance with second defective address information;

a third shift redundancy repairing circuit arranged corresponding to said plurality of second bit lines, for shifting and switching correspondence between said plurality of second bit lines and said plurality of second processing circuits in accordance with said first defective address information, and

a fourth shift redundancy repairing circuit arranged corresponding to said plurality of first bit lines, for shifting and switching correspondence between said plurality of first bit lines and said plurality of first processing circuits in accordance with said second defective address information.

14. The semiconductor device according to claim 8, further comprising

a data transfer circuit, provided corresponding to said plurality of second processing elements, for transferring data among said plurality of second processing elements with a data transfer path being changeable.

15. The semiconductor device according to claim 1, further comprising:

a plurality of bit lines, arranged corresponding to the respective memory columns of said memory cell array, each connected to memory cells of a corresponding column, said plurality of bit lines serving as said plurality of data transfer lines; and

a redundancy circuit arranged corresponding to said plurality of first processing circuits for repairing a defective processing circuit by shifting and changing connection correspondence between the data transfer lines and the first processing circuits.

16. The semiconductor device according to claim 1, further comprising:

a pointer circuit arranged common to respective entries of said memory cell array and designating an area in which significant data is stored in each entry, said pointer circuit designating an area for storing each multi-bit data when a plurality of multi bit data are stored in each of the entries.

17. A semiconductor device according to claim 1, wherein

each of said first processing elements includes a processor, first and second registers, and a mask register.

18. The semiconductor device according to claim 17, wherein

the second register stores a carry at a time of the operation of addition or subtraction;

and

said operational control unit stores the data stored in said second register to a corresponding bit position of a corresponding entry at completion of the operation.

19. The semiconductor device according to claim 17, wherein

said mask register stores a multiplicand bit in the operation of multiplication;

and

said operational control unit operates such that;

in accordance with the value stored in said mask register, addition of a multiplier bit of said corresponding entry and a multiplication result bit is performed selectively;

result of the addition operation is stored in said first register and written to an original position of a corresponding multiplication result storing area in the corresponding entry;

after selective addition of all bits of said multiplier;

a bit position address of said multiplicand bit is incremented and a bit position address of said multiplication result bit is incremented by one; and

similar operation is repeated on the multiplier, the bit position address indicating a bit location in the corresponding entry.

20. A semiconductor signal processing device, comprising:

a first processing unit;

an internal bus; and

a plurality of operation units each comprising an operational block and an operational control unit,

wherein each operational block includes;

a memory cell mat divided into a plurality of entries, each of which includes a plurality of memory cells;

a plurality of processing circuits, each of which couples with a corresponding entry and includes (i) a Booth register circuit for storing a result of decoding a set of data bits from a first area of the corresponding entry in accordance with second order Booth'"'"'s algorithm, (ii) a processor receiving data bits from corresponding bit positions of the second and third areas of the corresponding entry, and performing an operational processing on the data bits received in accordance with the data stored in said Booth register, and (iii) a result register storing an output data of said processor; and

a control circuit for transferring data from the first, second and third areas of each entry of said memory cell mat to each processing circuit corresponding to each entry for performing the operational processing, transferring and writing output data of said processor to the third area of the corresponding entry, and controlling the operational processing of the processing circuits,

wherein the operation of processing performed by the processor is one of plural operations designated by the control circuit.

21. The semiconductor signal processing device according to claim 20, wherein

said processor selectively performs, in accordance with the data value stored in said Booth register, on a set of data from said second and third areas, an operation of 1-bit shift or 2-bit shift, and inversion or non-inversion, and no operation of data from said second area, and adds a result of the operation to the data from said third area.

22. The semiconductor signal processing device according to claim 20, wherein

each of the entries includes an even-numbered entry for storing even-numbered bits and an odd numbered entry for storing odd-numbered bits, and

each processor receives, in parallel, data of corresponding bit positions of the even-numbered and odd-numbered entries of a corresponding entry and executes the operational processing.