Semiconductor device and semiconductor signal processing apparatus
First Claim
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1. A semiconductor device, comprising:
- a first processing unit;
an internal bus; and
,a plurality of operation units each comprising an operational block and an operational control unit,wherein said first processing unit issues an instruction to the operation units via said internal bus,wherein each operational block includes a memory array used for storing data and divided into plural entries, and a plurality of first processing elements each of which is arranged corresponding to a respective entry of said memory array and is for performing an arithmetic and logical operation,wherein each of said plural first processing elements performs an operation instructed by said operational control unit using data provided from first selected memory cells in corresponding entries in parallel and store result of said operation into second selected memory cells in said corresponding entries in parallel, andwherein said memory array has a first word line selected for activating the first selected memory cells of all the entries, and has a second word line selected for activating said second selected memory cells of all the entries.
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Abstract
A memory cell mat is divided into a plurality of entries, and an arithmetic logic unit is arranged corresponding to each entry. Between the entries and the corresponding arithmetic logic units, arithmetic/logic operation is executed in bit-serial and entry-parallel manner. Where parallel operation is not very effective, data is transferred in entry-serial and bit-parallel manner to a group of processors provided at a lower portion of the memory mat. In this manner, a large amount of data can be processed at high speed regardless of the contents of operation or data bit width.
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Citations
22 Claims
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1. A semiconductor device, comprising:
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a first processing unit; an internal bus; and
,a plurality of operation units each comprising an operational block and an operational control unit, wherein said first processing unit issues an instruction to the operation units via said internal bus, wherein each operational block includes a memory array used for storing data and divided into plural entries, and a plurality of first processing elements each of which is arranged corresponding to a respective entry of said memory array and is for performing an arithmetic and logical operation, wherein each of said plural first processing elements performs an operation instructed by said operational control unit using data provided from first selected memory cells in corresponding entries in parallel and store result of said operation into second selected memory cells in said corresponding entries in parallel, and wherein said memory array has a first word line selected for activating the first selected memory cells of all the entries, and has a second word line selected for activating said second selected memory cells of all the entries. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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20. A semiconductor signal processing device, comprising:
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a first processing unit; an internal bus; and a plurality of operation units each comprising an operational block and an operational control unit, wherein each operational block includes; a memory cell mat divided into a plurality of entries, each of which includes a plurality of memory cells; a plurality of processing circuits, each of which couples with a corresponding entry and includes (i) a Booth register circuit for storing a result of decoding a set of data bits from a first area of the corresponding entry in accordance with second order Booth'"'"'s algorithm, (ii) a processor receiving data bits from corresponding bit positions of the second and third areas of the corresponding entry, and performing an operational processing on the data bits received in accordance with the data stored in said Booth register, and (iii) a result register storing an output data of said processor; and a control circuit for transferring data from the first, second and third areas of each entry of said memory cell mat to each processing circuit corresponding to each entry for performing the operational processing, transferring and writing output data of said processor to the third area of the corresponding entry, and controlling the operational processing of the processing circuits, wherein the operation of processing performed by the processor is one of plural operations designated by the control circuit. - View Dependent Claims (21, 22)
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Specification