Memory system topologies including a buffer device and an integrated circuit memory device
First Claim
1. A system comprising:
- an integrated circuit buffer device including;
a first interface to receive write data and control information that indicates a write operation;
a second interface to convey the write data and the control information; and
a register to store a value that indicates a number of integrated circuit memory devices to receive, in response to the control information, the write data;
a first integrated circuit memory device to store a first portion of the write data;
a first signal path coupled to the second interface and the first integrated circuit memory device, the first signal path to convey the first portion of the write data from the integrated circuit buffer device to the first integrated circuit memory device;
a second integrated circuit memory device to store a second portion of the write data;
a second signal path coupled to the second interface and the second integrated circuit memory device, the second signal path to convey the second portion of the write data from the integrated circuit buffer device to the second integrated circuit memory device; and
a third signal path coupled to the integrated circuit buffer device and the first and second integrated circuit memory devices, the third signal path to convey the control information from the integrated circuit buffer device to both the first and second integrated circuit memory devices.
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Accused Products
Abstract
Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device. The buffer device segments and merges the data transferred between the memory controller that expects a particular memory organization and actual memory organization.
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Citations
10 Claims
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1. A system comprising:
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an integrated circuit buffer device including; a first interface to receive write data and control information that indicates a write operation; a second interface to convey the write data and the control information; and a register to store a value that indicates a number of integrated circuit memory devices to receive, in response to the control information, the write data; a first integrated circuit memory device to store a first portion of the write data; a first signal path coupled to the second interface and the first integrated circuit memory device, the first signal path to convey the first portion of the write data from the integrated circuit buffer device to the first integrated circuit memory device; a second integrated circuit memory device to store a second portion of the write data; a second signal path coupled to the second interface and the second integrated circuit memory device, the second signal path to convey the second portion of the write data from the integrated circuit buffer device to the second integrated circuit memory device; and a third signal path coupled to the integrated circuit buffer device and the first and second integrated circuit memory devices, the third signal path to convey the control information from the integrated circuit buffer device to both the first and second integrated circuit memory devices. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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Specification