System, method and computer program product for handling small aggressors in signal integrity analysis

• US 7,562,323 B1
• Filed: 05/04/2006
• Issued: 07/14/2009
• Est. Priority Date: 09/19/2003
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Bai, Xiaoliang, Keller, Igor
• Primary Examiner(s): GARBOWSKI, LEIGH M
• Application Number:
  US11/417,862
• Time in Patent Office: 1,167 Days
• Field of Search: None
• US Class Current: 716/115
• CPC Class Codes: G06F 30/3312 Timing analysis
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Abstract

A method, system and computer program product for determining aggressor-induced crosstalk in a victim net of a stage of an integrated circuit design is provided. The methodology can include combining a plurality of aggressor nets to construct a virtual aggressor net, determining a current waveform induced on the victim net by the plurality of small aggressor nets, and modeling a current waveform induced by the virtual aggressor on the victim net based on the contribution of the current waveforms determined for the plurality of small aggressor nets. In a further embodiment, the methodology can also comprise evaluating an effect of an aggressor net on a victim net; and including that aggressor net in the virtual aggressor net if its effect is below a predetermined threshold. The effect evaluated by the methodology can, for example, be the height of a glitch induced on the victim net by a transition in the aggressor net. Additionally, the aggressor net can be included in the virtual aggressor net if the height of the glitch it induces on the victim net is less than a predetermined factor of the supply voltage. Switching probability can be used to compute a 3-sigma capacitance value, and this value can be used to limit the number of small aggressors included in the virtual aggressor net. The combined currents of the aggressor in the virtual aggressor net can be modeled using a piece-wise linear analysis.

Claims

1. A method for determining capacitive aggressor-induced crosstalk in a victim net of a stage of an integrated circuit design, comprising:

evaluating, using a computer, an effect of each of multiple capacitive aggressor nets of the stage on the victim net to identify a plurality of capacitive aggressor nets each having an effect on the victim net below a threshold;

combining the identified plurality of capacitive aggressor nets of the stage to construct a virtual capacitive aggressor net of the stage;

determining current waveforms induced on the victim net by individual ones of the plurality of capacitive aggressor nets of the stage; and

modeling a current waveform induced by the virtual capacitive aggressor net of the stage on the victim net based on the contribution of the current waveforms determined for the plurality of capacitive aggressor nets of the stage.

2. The method of claim 1, wherein the effect evaluated is a height of a glitch induced on the victim net by a transition in the capacitive aggressor net of the stage.

3. The method of claim 2, wherein the capacitive aggressor net of the stage is included in the virtual capacitive aggressor net if the height of the glitch it induces on the victim net is less than a predetermined factor of the supply voltage.

4. The method of claim 1, wherein modeling the current waveform of the virtual capacitive aggressor comprises combining the current waveforms determined for the plurality of capacitive aggressor nets of the stage.

5. The method of claim 1, wherein modeling the current waveform of the virtual capacitive aggressor of the stage comprises combining the current waveforms of a plurality of small capacitive aggressors of the stage in a piecewise linear fashion.

6. The method of claim 1, wherein modeling the current waveform of the virtual capacitive aggressor of the stage comprises determining a virtual capacitive aggressor function ƒ

_va(T) such that

$f_{\mathrm{va}}<br><br>\left(T\right)=\frac{1}{C_{\mathrm{va}}}<br><br>{\int <br><br>}_0^T<br><br>\left(\underset{k=1}{\overset{n}{\sum <br><br>}}<br><br><br><br>C_k<br><br>\frac{d<br><br>f_k<br><br>\left(t\right)}{d<br><br>t}\right)<br><br>d<br><br>t,$

where Cva is the capacitance of the virtual capacitive aggressor, C_k is the capacitance of the k-th of n capacitive aggressors, and ƒ

k(t) is a voltage as a function of time for a transition on the k-th capacitive aggressor.

7. The method of claim 1, further comprising filtering the effects of the capacitive aggressor nets of the stage using time-window filtering.

8. The method of claim 7, wherein filtering comprises determining whether a capacitive aggressor net transition is within a predetermined temporal distance from a time of interest associated with the victim net.

9. The method of claim 7, wherein filtering comprises assuming a worst case scenario for a capacitive aggressor transition with the capacitive aggressor'"'"'s timing window.

10. The method of claim 1, further comprising accumulating coupling capacitance for the capacitive nets in the virtual capacitive aggressor and filtering the cumulative result by discarding a capacitance that is more than 3-σ

away from a Gaussian mean of a switching capacitance.

11. An article of manufacture including a computer readable storage medium storing computer program code for determining capacitive aggressor-induced crosstalk in a victim net of a stage of an integrated circuit design, the program code comprising instructions operable to cause a programmable processor to:

evaluate an effect of each of multiple capacitive aggressor nets of the stage on the victim net to identify a plurality of capacitive aggressor nets each having an effect on the victim net below a threshold;

combine the identified plurality of capacitive aggressor nets of the stage to construct a virtual capacitive aggressor net of the stage;

determine current waveforms induced on the victim net by individual ones of the plurality of capacitive aggressor nets of the stage;

and model a current waveform induced by the virtual capacitive aggressor net on the victim net based on the contribution of the current waveforms determined for the plurality of capacitive aggressor nets of the stage.

12. The article of claim 11, wherein the effect evaluated is a height of a glitch induced on the victim net by a transition in the capacitive aggressor net of the stage.

13. The article of claim 11, wherein the instructions operable to cause a programmable processor to model the current waveform of the virtual capacitive aggressor of the stage comprises instructions operable to cause a programmable processor to combine the current waveforms of a plurality of small capacitive aggressors.

14. The article of claim 11, wherein the program further comprises instructions operable to cause a programmable processor to filter the effects of the capacitive aggressor nets of the stage using time-window filtering.

15. The article of claim 14, wherein the instructions operable to cause a programmable processor to filter the effects of the capacitive aggressor nets of the stage comprise at least one of instructions operable to cause a programmable processor to determine whether a capacitive aggressor net transition is within a predetermined temporal distance from a time of interest associated with the victim net, instructions operable to cause a programmable processor to assume a worst case scenario for a capacitive aggressor transition with a capacitive aggressor'"'"'s timing window, and instructions operable to cause a programmable processor to accumulate the coupling capacitance for the capacitive aggressor nets of the stage in the virtual capacitive aggressor and filter the cumulative result by discarding a capacitance that is more than 3-0 away from a Gaussian mean of a switching capacitance.

16. A system comprising:

means for evaluating an effect of each of multiple capacitive aggressor nets of the stage on the victim net to identify a plurality of capacitive aggressor nets each having an effect on the victim net below a threshold;

means for combining the identified plurality of capacitive aggressor nets of the stage to construct a virtual capacitive aggressor net of the stage;

means for determining current waveforms induced on the victim net by individual ones of the plurality of capacitive aggressor nets of the stage; and

means for modeling a current waveform induced by the virtual capacitive aggressor net on the victim net based on the contribution of the current waveforms determined for the plurality of capacitive aggressor nets of the stage.

17. The system of claim 16, wherein the effect evaluated is a height of a glitch induced on the victim net by a transition in the capacitive aggressor net of the stage.

18. The system of claim 16, further comprising means for filtering the effects of the capacitive aggressor nets of the stage using time-window filtering.

19. The system of claim 18, wherein the means for filtering further comprises means for determining whether a capacitive aggressor net transition is within a predetermined temporal distance from a time of interest associated with the victim net.