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Scan engine with dual chip architecture for use in electro-optical readers

  • US 7,562,826 B2
  • Filed: 10/19/2005
  • Issued: 07/21/2009
  • Est. Priority Date: 09/12/2005
  • Status: Active Grant
First Claim
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1. A dual chip architecture for controlling electro-optical reading of indicia, comprising:

  • a) an application specific integrated circuit (ASIC) constituting a first chip on which are integrated a laser drive for energizing a laser to emit a laser beam toward the indicia, a scanner drive for sweeping the laser beam across the indicia for reflection therefrom, a receiver for receiving an analog received signal indicative of the laser beam reflected from the indicia, and a digitizer for digitizing the received signal to generate a digitized signal, at least one of the laser drive, the scanner drive, the receiver and the digitizer having an adjustable element;

    b) a microprocessor constituting a second chip operatively connected to the first chip and operative for generating a control signal for adjusting the adjustable element during reading, the microprocessor including a decoder for decoding the digitized signal into data corresponding to the indicia; and

    c) a single printed circuit board on which the first and second chips are commonly mounted.

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