Substrate having silicon germanium material and stressed silicon nitride layer

• US 7,563,680 B2
• Filed: 10/25/2007
• Issued: 07/21/2009
• Est. Priority Date: 01/15/2005
• Status: Expired due to Fees

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: Arghavani, Reza
• Primary Examiner(s): DANG, TRUNG Q
• Application Number:
  US11/924,564
• Publication Number:
  US 20080096356A1
• Time in Patent Office: 635 Days
• Field of Search: 438/275, 438/285, 257/E29.104, 257/E29.105, 257/E29.107
• US Class Current: 438/275
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02271 deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition H01L21/02266 takes precedence
• CPC Class Codes: H01L 21/3185 of siliconnitrides
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

A method of fabricating a semiconductor device includes providing a region having doped silicon region on a substrate, and forming a silicon germanium material adjacent to the region on the substrate. A stressed silicon nitride layer is formed over at least a portion of the doped silicon region on the substrate. The silicon germanium layer and stressed silicon nitride layer induce a stress in the doped silicon region of the substrate. In one version, the semiconductor device has a transistor with source and drain regions having the silicon germanium material, and the doped silicon region forms a channel that is configured to conduct charge between the source and drain regions. The stressed silicon nitride layer is formed over at least a portion of the channel, and can be a tensile or compressively stressed layer according the desired device characteristics.

Claims

1. A method of fabricating a semiconductor device, the method comprising:

(a) forming a doped silicon region in a substrate;

(b) forming a silicon germanium material adjacent to the doped silicon region to induce a stress in the doped silicon region;

(c) forming a counterdoped silicon region in the substrate between the silicon germanium material and the doped silicon region

(d) forming a stressed silicon nitride layer over at least a portion of the doped silicon region to further stress the doped silicon region; and

(e) forming a stressed dielectric layer over at least a portion of the stressed silicon nitride layer, the stressed dielectric layer having a tensile stress of at least about 200 MPa,

wherein the stressed silicon nitride layer induces a compressive stress having an absolute value of at least about 2.5 GPa.

2. A method according to claim 1 wherein (b) comprises epitaxially growing silicon germanium material on the substrate, the silicon germanium material having a chemical stoichiometry of Si_1-xGe_x, where x is from about 0.15 to about 0.3.

3. A method according to claim 1 wherein (b) comprises forming silicon germanium material having a chemical stoichiometry of Si_1-xGe_x, where x is selected to induce a stress of at least about 1 GPa in the doped silicon region.

4. A method according to claim 1 wherein (b) comprises forming a transistor having at least one of a source and a drain region that comprises the silicon germanium material.

5. A method according to claim 1, wherein the stressed silicon nitride layer induces a compressive stress.

6. A method according to claim 1 wherein the stressed silicon nitride layer induces a tensile stress.

7. A method according to claim 1, further comprising (f) forming a stressed silicon oxide layer adjacent to the silicon germanium material, wherein the stressed silicon oxide layer induces a tensile stress of at least about 800 MPa.

8. A method according to claim 1 further comprising (f) forming a stressed metal silicide layer over at least a portion of the silicon germanium material.

9. A method according to claim 7, wherein (f) comprises forming a trench to isolate the transistor in the substrate.

10. A method of fabricating a semiconductor device, the method comprising:

(a) forming a channel region comprised of germanium in a substrate;

(b) forming a silicon germanium material adjacent to the channel region to induce a stress in the channel region;

(c) forming a stressed silicon nitride layer over at least a portion of the channel region to further stress the channel region; and

(d) forming a stressed dielectric layer having a tensile stress of at least about 200 MPa over at least a portion of the stressed silicon nitride layer.

11. A method according to claim 10 wherein (b) comprises epitaxially growing silicon germanium material on the substrate, the silicon germanium material having a chemical stoichiometry of Si_1-x,Ge_x, where x is from about 0.15 to about 0.3.

12. A method according to claim 10 wherein (b) comprises forming silicon germanium material having a chemical stoichiometry of Si_1-x,Ge₊, where x is selected to induce a stress of at least about 1 GPa in the channel region.

13. A method according to claim 10 wherein (b) comprises forming a transistor having a source and drain, a channel between the source and drain, and a gate above the channel, and (b) comprises forming the silicon germanium material to extend throughout the source and drain.

14. A method according to claim 10 wherein (c) comprises forming a stressed silicon nitride layer comprising a compressive stress having an absolute value of at least about 2.5 GPa.

15. A method according to claim 10 wherein (c) comprises forming a stressed silicon nitride layer comprising a tensile stress of at least about 1.5 GPa.

16. A method according to claim 13 further comprising (d) forming a stressed silicon oxide layer surrounding at least part of the source and drain, stressed silicon oxide layer having a tensile stress of at least about 800 MPa.

17. A method according to claim 10 further comprising (d) forming a stressed metal silicide layer over at least a portion of the silicon germanium material.

18. A method according to claim 15, wherein (d) comprises forming a trench to isolate the transistor in the substrate.