Gettering using voids formed by surface transformation

• US 7,564,082 B2
• Filed: 11/30/2006
• Issued: 07/21/2009
• Est. Priority Date: 07/21/2003
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Forbes, Leonard, Geusic, Joseph E.
• Primary Examiner(s): Quach; Tuan N.
• Application Number:
  US11/606,503
• Publication Number:
  US 20070080335A1
• Time in Patent Office: 964 Days
• Field of Search: 257/3, 257/288, 257/368, 257/387, 257/617, 257/E27.06, 257/913, 257/E21.318, 257/E29.255
• US Class Current: 257/288
• CPC Class Codes: H01L 21/3223 using cavities formed by hydrogen or noble gas ion implantation
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: Y10S 257/913 with means to absorb or localize unwanted impurities or defects from semiconductors, e.g. heavy metal gettering

Abstract

One aspect of this disclosure relates to a semiconductor structure, comprising a gettering region proximate to a device region in a semiconductor wafer. The gettering region includes a precisely-determined arrangement of a plurality of precisely-formed voids through a surface transformation process. Each of the voids has an interior surface that includes dangling bonds such that the plurality of voids getter impurities from the at least one device region. The structure includes a transistor formed using the device region. The transistor includes a gate dielectric over the device region, a gate over the gate dielectric, and a first diffusion region and a second diffusion region formed in the device region. The first and second diffusion regions are separated by a channel region formed in the device region between the gate and the proximity gettering region.

Claims

1. A semiconductor structure, comprising:

a gettering region formed proximate to a device region in a semiconductor material;

the gettering region including an arrangement of a plurality of voids having a predetermined void-to-void spacing, wherein each void has a shape and size formed through a surface transformation process, and wherein the surface transformation process includes;

forming holes or trenches with predetermined dimensions and spacing though a surface of the semiconductor material;

annealing the semiconductor material to transform the holes or trenches through the surface of the semiconductor material into the arrangement of the voids with the predetermined void-to-void spacing, wherein the void-to-void spacing and the shape and size of each void is controlled by the predetermined dimensions and spacing of the holes or trenches,

each of the voids having an interior surface that includes dangling bonds such that the plurality of voids getter impurities from the at least one device region; and

a transistor formed using the device region, the transistor including

a gate dielectric over the device region;

a gate over the gate dielectric; and

a first diffusion region and a second diffusion region formed in the device region, the first and second diffusion regions being separated by a channel region formed in the device region between the gate and the proximity gettering region.

2. The structure of claim 1, wherein the plurality of voids are separated by a critical length (λ

_c) that is dependent on the radius (R_c) of a number of holes used to form the plurality of voids using the surface transformation process.

3. The structure of claim 1, wherein the arrangement of a plurality of voids is uniformly distributed through the at least one gettering region.

4. The structure of claim 1, wherein the gettering region has a volume, and the arrangement of the plurality of voids is formed to provide a large ratio between the interior surface of the plurality of voids and the volume to enhance gettering.

5. The structure of claim 1, wherein the plurality of voids includes a sphere-shaped void.

6. The structure of claim 1, wherein the plurality of voids includes a pipe-shaped void.

7. The structure of claim 1, wherein the plurality of voids includes a plate-shaped void.

8. The structure of claim 1, wherein the gettering region is below the device region.

9. A semiconductor structure, comprising:

a gettering region formed proximate to a device region in a semiconductor material;

the gettering region including an arrangement of a plurality of voids having a predetermined void-to-void spacing, wherein each void has a shape and size formed through a surface transformation process, and wherein the transformation process includes;

forming holes with predetermined dimensions and spacing through a surface of the semiconductor material;

annealing the semiconductor material to transform the holes into the arrangement of the voids with the predetermined void-to-void spacing,

each of the voids having an interior surface that includes dangling bonds such that the plurality of voids getter impurities from the at least one device region, wherein the plurality of voids are separated by a critical length (λ

_c) that is dependent on the radius (R_c) of a number of holes used to form the plurality of voids using the surface transformation process, and the plurality of voids includes a sphere-shaped void;

a transistor formed using the device region, the transistor including

a gate dielectric over the device region;

a gate over the gate dielectric; and

a first diffusion region and a second diffusion region formed in the device region, the first and second diffusion regions being separated by a channel region formed in the device region between the gate and the proximity gettering region.

10. The structure of claim 9, wherein the arrangement of a plurality of voids is uniformly distributed through the gettering region.

11. The structure of claim 9, wherein the gettering region has a volume, and the arrangement of the plurality of voids is formed to provide a large ratio between the interior surface of the plurality of voids and the volume to enhance gettering.

12. The structure of claim 9, wherein the gettering region is below the device region.

13. A semiconductor structure, comprising:

a gettering region formed proximate to a device region in a semiconductor material;

the gettering region including an arrangement of a plurality of voids having a predetermined void-to-void spacing, wherein each void has a shape and size formed through a surface transformation process, and wherein the surface transformation process includes;

forming holes with predetermined dimensions and spacing through a surface of the semiconductor material;

annealing the semiconductor material to transform the holes into the arrangement of voids with the predetermined void-to-void spacing,

each of the voids having an interior surface that includes dangling bonds such that the plurality of voids getter impurities from the at least one device region, wherein the plurality of voids are separated by a critical length (λ

_c) that is dependent on the radius (R_c) of a number of holes used to form the plurality of voids using the surface transformation process, and the plurality of voids includes a pipe-shaped void; and

a transistor formed using the device region, the transistor including

a gate dielectric over the device region;

a gate over the gate dielectric; and

a first diffusion region and a second diffusion region formed in the device region, the first and second diffusion regions being separated by a channel region formed in the device region between the gate and the proximity gettering region.

14. The structure of claim 13, wherein the arrangement of a plurality of voids is uniformly distributed though the gettering region.

15. The structure of claim 13, wherein the gettering region has a volume, and the arrangement of the plurality of voids is formed to provide a large ratio between the interior surface of the plurality of voids and the volume to enhance gettering.

16. The structure of claim 13, wherein the gettering region is below the device region.

17. A semiconductor structure, comprising:

a gettering region formed proximate to a device region in a semiconductor material;

the gettering region including an arrangement of a plurality of voids having a predetermined void-to-void spacing, wherein each void has a shape and size formed through a surface transformation process, and wherein the surface transformation process includes;

forming holes with predetermined dimensions and spacing through a surface of the semiconductor material;

annealing the semiconductor material to transform the holes into the arrangement of voids with the predetermined void-to-void spacing,

wherein the arrangement of voids includes voids with a size, shape and spacing controlled by the predetermined dimensions and spacing of the holes, each of the voids having an interior surface that includes dangling bonds such that the plurality of voids getter impurities from the at least one device region, wherein the plurality of voids are separated by a critical length (λ

_c) that is dependent on the radius (R_c) of a number of holes used to form the plurality of voids using the surface transformation process, and the plurality of voids includes a plate-shaped void; and

a transistor formed using the device region, the transistor including

a gate dielectric over the device region;

a gate over the gate dielectric; and

a first diffusion region and a second diffusion region formed in the device region, the first and second diffusion regions being separated by a channel region formed in the device region between the gate and the proximity gettering region.

18. The structure of claim 17, wherein the arrangement of a plurality of voids is uniformly distributed through the gettering region.

19. The structure of claim 17, wherein the gettering region has a volume, and the arrangement of the plurality of voids is formed to provide a large ratio between the interior surface of the plurality of voids and the volume to enhance gettering.

20. The structure of claim 17, wherein the gettering region is below the device region.