Semiconductor device and its manufacturing method

• US 7,564,102 B2
• Filed: 03/07/2003
• Issued: 07/21/2009
• Est. Priority Date: 03/15/2002
• Status: Active Grant

• Current Assignee: Godo Kaisha IP Bridge 1 (IP Bridge, Inc.)
• Original Assignee: NEC Corporation, Seiko Epson Corporation (Seiko Group)
• Inventors: Yoshihara, Takuya
• Primary Examiner(s): Monbleau; Davienne
• Assistant Examiner(s): Harrison; Monica D
• Application Number:
  US10/507,615
• Publication Number:
  US 20050110098A1
• Time in Patent Office: 2,328 Days
• Field of Search: 257/407, 257/574, 257/555, 257/525, 257/512, 257/511, 257/371, 257/369, 257/357, 257/351, 257/350, 257/338, 257/274, 257/206, 257/E31.085, 438/592
• US Class Current: 257/369
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants

Abstract

A method for manufacturing a semiconductor device wherein both the threshold voltages of an N-type MISFET and a P-type MISFET are low, device can be easily manufactured at a lower cost and a higher product yield, and the reliability of the gate insulation film is higher. The gate insulation film is formed on the surface of a silicon substrate 1 in N-type MISFET forming region and the P-type MISFET forming region, and metal gates 4 and 5 are provided thereon. The metal gate 4 is made from a TiCoN film, and the work function thereof is set at 4.0 to 4.8 eV suited to the gate electrode material of the N-type MISFET. The metal gate 5 is formed from a portion of the TiCoN film by ion-implantation of oxygen into the TiCoN film configuring the gate electrode 4 at a dosage of 1013 to 1014 (ions/cm2) to raise the work function by around 0.2 to 0.8 eV.

Claims

1. A semiconductor device comprising an N-channel metal-insulator-semiconductor field-effect transistor and a P-channel metal-insulator-semiconductor field-effect transistor, characterized in that said N-channel metal-insulator-semiconductor field-effect transistor includes a gate electrode made of a metal, alloy or metal nitride film doped with oxygen or fluorine, and that said P-channel metal-insulator-semiconductor field-effect transistor includes a gate electrode formed in a common layer with said gate electrode of said N-channel metal-insulator-semiconductor field-effect transistor and made from a portion of said common layer doped with oxygen or fluorine more heavily than said gate electrode of said N-channel metal-insulator-semiconductor field-effect transistor.

3. The semiconductor device according to any one of claims 1 or 2, wherein a material configuring said gate electrode of said N-channel metal-insulator-semiconductor field-effect transistor and said gate electrode of said P-channel metal-insulator-semiconductor field-effect transistor is polycrystalline or amorphous and has an average grain size of 50 nm or less.

4. The semiconductor device according to any one of claims 1 or 2, wherein a material configuring said gate electrode of said N-channel metal-insulator-semiconductor field-effect transistor and said gate electrode of said P-channel metal-insulator-semiconductor field-effect transistor is made of an alloy including two or more metals selected from the group consisting of Al, Si, Ti, V, Co, Ni, Ge, Zr, Nb, Mo, Ru, Hf, Ta and W or a nitride of said alloy.

5. The semiconductor device according to claim 4, wherein said material configuring said gate electrode is made of said nitride of said alloy including Ti and a metal selected from the group consisting of Al, Si, V, Co, Ni, Ge, Zr, Nb, Mo, Ru, Hf, Ta and W.

6. The semiconductor device according to 5, wherein said material configuring said gate electrode is made of TiCoN or TiWN.

7. The semiconductor device according to claim 5, wherein said material configuring said gate electrode of said N-channel metal-insulator-semiconductor field-effect transistor and said gate electrode of said P-channel metal-insulator-semiconductor field-effect transistor is a nitride of an alloy including two or more metals selected from the group consisting of Al, Hf and Zr.

8. The semiconductor device according to claim 7, wherein a material configuring said gate electrode of said N-channel metal-insulator-semiconductor field-effect transistor and said gate electrode of said P-channel metal-insulator-semiconductor field-effect transistor is HfZrN.

9. The semiconductor device according to any one of claims 1 or 2, wherein an oxygen or fluorine profile of said gate electrode of said P-channel metal-insulator-semiconductor field-effect transistor with respect to a thickness direction thereof has a peak within 5 nm from an interface with said gate insulation film.

10. The semiconductor device according to any one of claims 1 or 2, wherein a work function of a material configuring said gate electrode of said P-channel metal-insulator-semiconductor field-effect transistor is 0.1 eV higher than a work function of a material configuring said gate electrode of said N-channel metal-insulator-semiconductor field-effect transistor.

11. The semiconductor device according to claim 3, wherein a material configuring said gate electrode of said N-channel metal-insulator-semiconductor field-effect transistor and said gate electrode of said P-channel metal-insulator-semiconductor field-effect transistor is made of an alloy including two or more metals selected from the group consisting of Al, Si, Ti, V, Co, Ni, Ge, Zr, Nb, Mo, Ru, Elf, Ta and W or a nitride of said alloy.

12. The semiconductor device according to claim 5, wherein an oxygen or fluorine profile of said gate electrode of said P-channel metal-insulator-semiconductor field-effect transistor with respect to a thickness direction thereof has a peak within 5 nm from an interface with said gate insulation film.

13. The semiconductor device according to claim 6, wherein an oxygen or fluorine profile of said gate electrode of said P-channel metal-insulator-semiconductor field-effect transistor with respect to a thickness direction thereof has a peak within 5 nm from an interface with said gate insulation film.

14. The semiconductor device according to claim 7, wherein an oxygen or fluorine profile of said gate electrode of said P-channel metal-insulator-semiconductor field-effect transistor with respect to a thickness direction thereof has a peak within 5 nm from an interface with said gate insulation film.

15. The semiconductor device according to claim 8, wherein an oxygen or fluorine profile of said gate electrode of said P-channel metal-insulator-semiconductor field-effect transistor with respect to a thickness direction thereof has a peak within 5 nm from an interface with said gate insulation film.

16. The semiconductor device according to claim 5, wherein a work function of a material configuring said gate electrode of said P-channel metal-insulator-semiconductor field-effect transistor is 0.1 eV higher than a work function of a material configuring said gate electrode of said N-channel metal-insulator-semiconductor field-effect transistor.

17. The semiconductor device according to claim 6, wherein a work function of a material configuring said gate electrode of said P-channel metal-insulator-semiconductor field-effect transistor is 0.1 eV higher than a work function of a material configuring said gate electrode of said N-channel metal-insulator-semiconductor field-effect transistor.

18. The semiconductor device according to claim 7, wherein a work function of a material configuring said gate electrode of said P-channel metal-insulator-semiconductor field-effect transistor is 0.1 eV higher than a work function of a material configuring said gate electrode of said N-channel metal-insulator-semiconductor field-effect transistor.

19. The semiconductor device according to claim 8, wherein a work function of a material configuring said gate electrode of said P-channel metal-insulator-semiconductor field-effect transistor is 0.1 eV higher than a work function of a material configuring said gate electrode of said N-channel metal-insulator-semiconductor field-effect transistor.

2. A semiconductor device comprising an N-channel metal-insulator-semiconductor field-effect transistor and a P-channel metal-insulator-semiconductor field-effect transistor, characterized in that said N-channel metal-insulator-semiconductor field-effect transistor includes a gate electrode made from a metal, alloy or metal nitride film, and that said P-channel metal-insulator-semiconductor field-effect transistor includes a gate electrode formed in a common layer with said gate electrode of said N-channel metal-insulator-semiconductor field-effect transistor and made from a portion of said common layer doped with oxygen or fluorine.