Differential output driver

• US 7,564,270 B1
• Filed: 06/27/2007
• Issued: 07/21/2009
• Est. Priority Date: 05/30/2007
• Status: Active Grant

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Ansel, George, Zhang, Xiaohu
• Primary Examiner(s): Tan, Vibol
• Application Number:
  US11/769,088
• Time in Patent Office: 755 Days
• Field of Search: 326/127, 326/115, 326/112, 326/121, 327/108, 327/109
• US Class Current: 326/127
• CPC Class Codes: H03K 19/00315 in field-effect transistor circuits
• CPC Class Codes: H03K 19/00384 in field effect transistor circuits

Abstract

A driver circuit is provided herein. In general, the driver circuit includes a driver portion, a common mode feedback portion and a current replication portion. The feedback portion receives a common mode voltage (vcm) from the driver portion and an alternative common mode voltage (vcm_alt) from the current replication portion. The feedback portion selects one of the common mode voltages for comparison with a reference voltage and generates a feedback bias signal (vcmfb) based on a voltage difference there between. When the driver circuit is enabled, the actual common mode voltage (vcm) is used to maintain the output common mode voltage around the reference voltage. When the driver circuit is disabled, the alternative common mode voltage (vcm_alt) is used to keep the bias signal (vcmfb) from drifting away.

Claims

1. A method for operating a driver circuit, the method comprising:

generating a first common mode voltage and a second common mode voltage;

selecting the first common mode voltage or the second common mode voltage, depending on an operating state of the driver circuit, wherein said selecting comprises selecting the first common mode voltage when the driver circuit is enabled and selecting the second common mode voltage when the driver circuit is disabled;

comparing the selected common mode voltage to a reference voltage; and

supplying a feedback signal to the driver circuit based on a difference detected in the comparison step.

2. The method as recited in claim 1, wherein the step of generating comprises generating the first and second common mode voltages at substantially the same time.

3. The method as recited in claim 1, wherein the steps of generating, selecting, comparing and supplying enable a predictable feedback signal to be supplied to the driver circuit when the driver circuit is disabled.

4. A driver circuit, comprising:

a feedback portion configured to receive a first common mode voltage from a driver portion and a second common mode voltage from a replication portion of the driver circuit, wherein the feedback portion comprises;

a selection circuit configured to select;

(i) the first common mode voltage when the driver portion is enabled, and (ii) the second common mode voltage when the driver portion is disabled; and

a comparator configured to compare the selected common mode voltage to a reference voltage and to supply a feedback signal to the driver portion based on a difference detected there between.

5. The driver circuit as recited in claim 4, wherein the feedback portion receives the first and second common mode voltages at substantially the same time.

6. The driver circuit as recited in claim 4, wherein the driver portion comprises a transistor switchbox coupled in series between a first current source and a first current sink, and wherein the transistor switchbox comprises a first pair of series-connected transistors coupled in parallel with a second pair of series-connected transistors.

7. The driver circuit as recited in claim 6, wherein the first common mode voltage is generated between a first pair of resistive elements coupled in series between output nodes of the driver portion.

8. The driver circuit as recited in claim 7, wherein the driver portion is:

(i) enabled when a first set of input signals are supplied to the transistor switchbox for turning on opposite transistors within the first and second pairs of series-connected transistors and directing driver output current through an off-chip resistive element coupled between the output nodes, and (ii) disabled when a second set of input signals are supplied to the transistor switchbox for turning off all transistors within the first and second pairs of series-connected transistors.

9. The driver circuit as recited in claim 8, wherein the replication portion comprises a second pair of resistive elements coupled in series between a second current source and a second current sink.

10. The driver circuit as recited in claim 9, wherein the second current source and second current sink are substantially identical to the first current source and first current sink, respectively, and wherein a combined resistance of the second pair of resistive elements is substantially identical to a resistance of the off-chip resistive element.

11. The driver circuit as recited in claim 9, wherein the second common mode voltage is generated between the second pair of resistive elements.

12. The driver circuit as recited in claim 4, wherein the comparator comprises:

a first transistor configured to receive the selected common mode voltage;

a second transistor configured to receive the reference voltage;

a bias transistor coupled between ground and mutually-connected terminals of the first and second transistors; and

a current mirror configured to generate the feedback signal by comparing a current generated through the first transistor to a current generated through the second transistor.

13. The driver circuit as recited in claim 12, wherein the selection circuit comprises a 2:

1 multiplexer having two inputs configured to receive the first and second common mode voltages and one output configured to supply the selected common mode voltage to the first transistor based on a control signal supplied to the multiplexer.

14. The driver circuit as recited in claim 4, wherein the comparator comprises:

a first transistor configured to receive the first common mode voltage;

a second transistor configured to receive the reference voltage;

a third transistor configured to receive the second common mode voltage;

a bias transistor coupled between ground and mutually-connected terminals of the first, second and third transistors; and

a current mirror configured to generate the feedback signal by comparing a current generated through the second transistor to a current generated through only one of the first and third transistors.

15. The driver circuit as recited in claim 14, wherein the selection circuit comprises a switch configured to connect the current mirror to either the first transistor or the third transistor, depending on a control signal supplied to the switch.

16. The driver circuit as recited in claim 15, wherein the switch comprises:

a fourth transistor coupled in series between the first transistor and a diode-connected transistor of the current mirror; and

a fifth transistor coupled in series between the third transistor and the diode-connected transistor.

17. A system, comprising:

at least one system component configured for generating a pair of differential signals;

a transmitter configured to modulate the differential signals before the modulated signals are driven across a transmission path to a receiver, wherein the transmitter comprises;

a driver portion configured to modulate the differential signals and to generate a first common mode voltage of the modulated signals;

a replication portion configured to generate a second common mode voltage;

a selection portion configured to select the first common mode voltage or second common mode voltage; and

a feedback portion configured to compare the selected common mode voltage to a reference voltage and to supply a feedback signal to the driver portion based on a difference detected there between.

18. The system as recited in claim 17, wherein the selection portion is configured for selecting the first common mode voltage when the driver portion is enabled and the second common mode voltage when the driver portion is disabled.

19. The system as recited in claim 17, further comprising a pair of output nodes configured to supply the modulated signals to the transmission path when the driver portion is enabled.

20. The system as recited in claim 19, wherein unlike the driver portion, the replication portion is disconnected from the output nodes, so that the second common mode voltage is unaffected by loads coupled to a receiving end of the transmission path when the driver portion is disabled.

21. The system as recited in claim 17, wherein the driver portion is configured for modulating the differential signals in accordance with an interface standard selected from a group comprising Low Voltage Differential Signaling (LVDS), Stub Series Terminated Logic (SSTL), differential High-Speed Transceiver Logic (HSTL) and Low Voltage Positive Referenced Emitter Coupled Logic (LFPECL).