Apparatus and method for configurable power management

• US 7,564,727 B1
• Filed: 06/25/2007
• Issued: 07/21/2009
• Est. Priority Date: 06/25/2007
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Huang, Jinsong Oliver
• Primary Examiner(s): Tan; Vibol
• Application Number:
  US11/821,811
• Time in Patent Office: 757 Days
• Field of Search: 326 38- 41, 713/320, 713/323, 713/324, 365/195, 365/185.04, 365/185.09, 711/2, 711/5, 711/114
• US Class Current: 365/195
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: H03K 19/17772 for powering on or off
• CPC Class Codes: H03K 19/17784 for supply voltage

Abstract

A method and apparatus to facilitate low-power consumption through a configurable suspend mode of operation of a PLD, the PLD comprising an application logic block coupled to receive configuration data bits and adapted to implement a logic application in response to the configuration data bits, a suspend pin coupled to receive a suspend signal, a write protect block coupled to the application logic block and adapted to prohibit the application logic block from changing logic states in response to a suspend mode initiated by the suspend signal; and an awake pin adapted to provide an awake signal that is indicative of a status of the suspend mode.

Claims

1. An integrated circuit device, comprising:

an application logic block coupled to receive configuration data bits and adapted to implement a logic application in response to the configuration data bits;

a suspend pin coupled to receive a suspend signal;

a write protect block coupled to the application logic block and adapted to prohibit the application logic block from changing logic states in response to a suspend mode initiated by the suspend signal;

an awake pin adapted to provide an awake signal that is indicative of a status of the suspend mode; and

a first multiplexer coupled to receive the suspend signal and adapted to allow propagation of the suspend signal within the integrated circuit device in response to a first logic state of a suspend enable signal.

2. The integrated circuit device of claim 1, wherein the application logic block comprises writable clocked elements that are disabled in response to the suspend signal, wherein the logic application is preserved during the suspend mode.

3. The integrated circuit device of claim 2, wherein the writable clocked elements are enabled in response to the awake signal.

4. The integrated circuit device of claim 1, wherein the first multiplexer is adapted to disallow propagation of the suspend signal within the programmable logic device in response to a second logic state of the suspend enable signal.

5. The integrated circuit device of claim 4, further comprising a filter coupled to the first multiplexer and adapted to provide a filtered suspend signal to prohibit an unintended initiation of the suspend mode within the programmable logic device.

6. The integrated circuit device of claim 5, further comprising a second multiplexer having an input coupled to the filter and adapted to allow propagation of the filtered suspend signal within the programmable logic device in response to a first logic state of a filter enable signal.

7. The integrated circuit device of claim 6, wherein the second multiplexer is adapted to disallow propagation of the filtered suspend signal within the programmable logic device in response to a second logic state of the filter enable signal.

8. The integrated circuit device of claim 1, further comprising an input block coupled to the application logic block, the input block being prohibited from providing inputs to the application logic block in response to the suspend mode.

9. The integrated circuit device of claim 1, further comprising an output block coupled to the application logic block, the output block being prohibited from accepting outputs from the application logic block in response to the suspend mode.

10. The integrated circuit device of claim 1, further comprising a configurable output driver having an output coupled to the awake pin and an output enable coupled to receive the awake signal, the output driver being configured to conduct current from the awake pin in response to a first logic state of the awake signal.

11. The integrated circuit device of claim 1, further comprising a configurable output driver having an output coupled to the awake pin and an input coupled to receive the awake signal, the output driver being configured to provide the awake signal to the awake pin.

12. A method of implementing configurable power management within an integrated circuit, the method comprising:

configuring an application logic block within the integrated circuit to execute a logic application;

activating a suspend mode within the integrated circuit;

suspending operation of the application logic block while the suspend mode is active, wherein the configuration and application state of the application logic block is preserved during the suspend mode; and

configuring an output driver of the integrated circuit to allow deactivation of the suspend mode, wherein operation of the application logic block is resumed in response to the deactivated suspend mode without requiring a reconfiguration of the application logic block.

13. The method of claim 12, wherein activating the suspend mode comprises:

downloading configuration data bits to the integrated circuit; and

storing the configuration data bits within configuration memory cells to configure the integrated circuit to initiate the suspend mode in response to a suspend signal.

14. The method of claim 12, wherein suspending operation of the application logic block comprises preventing elements within the application logic block from changing logic states.

15. The method of claim 12, further comprising:

disabling an input block of the integrated circuit in response to the suspend mode; and

disabling an output block of the integrated circuit in response to the suspend mode.

16. The method of claim 12, wherein configuring the output driver comprises:

downloading configuration data bits to the integrated circuit;

storing the configuration data bits within configuration memory cells to configure the output driver as an active output driver; and

providing an awake signal to an output pin of the integrated circuit using the output driver to initiate a wake-up process in response to the deactivated suspend mode.

17. The method of claim 12, wherein configuring the output driver comprises:

downloading configuration data bits to the integrated circuit;

storing the configuration data bits within configuration memory cells to configure the output driver as an open-drain output driver; and

providing an awake signal to enable an output of the open-drain output driver to allow a device external to the integrated circuit to initiate a wake-up process in response to the deactivated suspend mode.

18. A configurable power management system, comprising:

a plurality of programmable logic devices coupled together at a first node, each programmable logic device including,

an application logic block coupled to receive configuration data bits and adapted to implement a logic application in response to the configuration data bits;

a suspend pin coupled to receive a suspend signal;

a write protect block coupled to the application block and adapted to prohibit the application block from changing logic states in response to a suspend mode initiated by the suspend signal;

an output driver coupled to receive an awake signal from within the programmable logic device, wherein an output of the output driver is disabled in response to the awake signal; and

an awake pin coupled to the output of the output driver; and

an external device coupled to the first node, the external device adapted to assert a logic level at the first node to allow the plurality of programmable logic devices to synchronously recover from the suspend mode after each output driver of each programmable logic device is disabled.

19. The configurable power management system of claim 18, wherein the external device includes a resistor having a first conductor coupled to the first node and a second conductor coupled to a power supply.