Telecommunications receiver with automatic gain control

• US 7,565,125 B2
• Filed: 06/23/2003
• Issued: 07/21/2009
• Est. Priority Date: 12/18/2002
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Roussel, Vincent, Audinot, Pascal
• Primary Examiner(s): Urban; Edward
• Assistant Examiner(s): Hannon; Christian A
• Application Number:
  US10/601,348
• Publication Number:
  US 20040259510A1
• Time in Patent Office: 2,220 Days
• Field of Search: 455/232.1, 455/234.1, 455/245.1, 455227-229, 455/234.2, 375/345, 375/346, 375/350
• US Class Current: 455/234.2
• CPC Class Codes: H03G 3/3052 in bandpass amplifiers (H.F. or I.F.) or in frequency-changers used in a (super)heterodyne receiver H03G3/32, H03G3/34 take precedence
• CPC Class Codes: H03G 3/3068 Circuits generating control signals for both R.F. and I.F. stages
• CPC Class Codes: H03M 1/183 the feedback signal controlling the gain of an amplifier or attenuator preceding the analogue/digital converter

Abstract

A receiver 30 has an adjustable gain control circuit 32 that provides gain control base on the magnitude of the signal at the input of an analog-to-digital converter 22. The magnitude of a gain increase or decrease can be based on the most significant bits of the analog-to-digital output, indicating whether the analog-to-digital converter is close to saturation, approaching saturation, or well below saturation.

Claims

1. A receiver comprising:

analog-to-digital circuitry for generating a digital representation, comprising a bit signal, of an amplified analog signal at an input;

adjustable gain control circuitry for receiving a radio signal and outputting the amplified analog signal using a gain determined by a magnitude of the amplified analog signal, the gain being connected directly to the bit signal at an output of the analog-to-digital circuitry;

digital channel filtering circuitry for filtering said digital representation; and

digital processing circuitry for processing the output of said digital channel filtering circuitry,

wherein the gain is adjusted by a first amount responsive to a first bit selected from a predetermined plurality of most significant bits in the bit signal, the first bit indicating that the output of the analog-to-digital circuitry has exceeded a first saturation threshold,

wherein the gain is adjusted by a second amount responsive to a first set of bits selected from the predetermined plurality of most significant bits in the bit signal, the first set of bits indicating that the output of the analog-to-digital circuitry has exceeded a second saturation threshold,

wherein the first amount is not equal to the second amount, and

wherein the first saturation threshold is not equal to the second saturation threshold.

2. The receiver of claim 1 wherein said adjustable gain control circuitry adjusts said gain independent of said digital processing circuitry.

3. The receiver of claim 1 wherein said gain is adjusted by a third amount responsive to a second set of bits selected from the predetermined plurality of most significant bits of said bit signal, the second set of bits indicating that the output of the analog-to-digital circuitry is below a third saturation threshold.

4. The receiver of claim 3 wherein the third amount represents an increase in the gain.

5. The receiver of claim 1 wherein the first bit is the most significant bit of the predetermined plurality of most significant bits, the first bit indicating that the output of the analog-to-digital converter has exceeded the first saturation threshold, and wherein the first bit signal is directly connected to a gain control input of the adjustable gain control circuitry.

6. The receiver of claim 1 wherein said gain is adjusted by the first amount using the output of the analog-to-digital circuitry without intervention from the digital processing circuitry if the output of the analog-to-digital circuitry is close to saturation over the first saturation threshold.

7. The receiver of claim 1 wherein both the first and the second amounts represent a decrease in the gain.

8. A method of receiving a signal in a receiver, comprising the steps of:

generating a digital representation of a signal at an output of an analog-to-digital converter after applying a gain to the signal;

adjusting the gain by a magnitude of the signal, the gain being directly connected and responsive to bit values of the digital representation of said output of said analog-to-digital converter;

generating a filtered digital representation for a desired channel; and

processing the filtered digital representation,

wherein adjusting the gain comprises

adjusting the gain by a first predetermined amount responsive to a first bit selected from a predetermined plurality of most significant bits from the bit values of the digital representation, the first bit indicating that the output of the analog-to-digital converter has exceeded a first saturation threshold, and

adjusting the gain by a second predetermined amount responsive to a first set of bits selected from the predetermined plurality of most significant bits from the bit values of the digital representation, the first set of bits indicating that the output of the analog-to-digital converter has exceeded a second saturation threshold,

wherein the first predetermined amount and the second predetermined amount are not equal, and

wherein the first saturation threshold is not equal to the second saturation threshold.

9. The method of claim 8 wherein said adjusting the gain by the first predetermined amount is performed using the output of the analog-to-digital converter without intervention from a digital processor if the output of the analog-to-digital converter is close to saturation over the first saturation threshold.

10. The method of claim 8 wherein both the first and second predetermined amounts represent a decrease in the gain.

11. The method of claim 8 wherein adjusting the gain further comprises adjusting the gain by a third amount responsive to a second set of bits selected from the predetermined plurality of most significant bits from said bit values of the digital representation, the second set of bits indicating that the output of the analog-to-digital converter has fallen below a third saturation threshold.

12. The method of claim 11 wherein the third amount represents an increase in the gain.

13. A receiver comprising:

adjustable gain control circuitry for receiving a radio signal and outputting an amplified analog signal using a gain determined by a magnitude of the amplified analog signal. the gain being connected directly to a single bit sample of a digital representation signal at an output of an analog-to-digital circuitry;

digital channel filtering circuitry for filtering said digital representation; and

digital processing circuitry for processing the output of said digital channel filtering circuitry,

wherein the gain is operable to be adjusted by a first amount responsive to a first bit selected from a predetermined plurality of most significant bits in the single bit sample of the digital representation signal, the first hit indicating that the output of the analog-to-digital circuitry has exceeded a first saturation threshold,

wherein the gain is operable to be adjusted by a second amount, responsive to a first set of bits selected from the predetermined plurality of most significant bits in the single bit sample of the digital representation signal, the first set of bits indicating that the output of the analog-to-digital circuitry has exceeded a second saturation threshold,

wherein the first amount and the second amount are not equal, and

wherein the first saturation threshold is not equal to the second saturation threshold.

14. The receiver of claim 13 wherein said adjustable gain control circuitry is coupled to receive an output signal from at least one low pass filter.

15. The receiver of claim 14 wherein at least one input of said at least one low pass filter is coupled to an output of at least one mixer.

16. The receiver of claim 15 wherein at least one input of said at least one mixer is coupled to an output of an amplifier.

17. The receiver of claim 16 wherein an input of said amplifier is coupled to an output of a bandpass filter.

18. receiver of claim 14 wherein said at least one low pass fitter comprises two low pass filters.

19. The receiver of claim 13 wherein said adjustable gain control circuitry comprises two gain control circuits, whereby both sensitivity and interference tests may be conducted.

20. The receiver of claim 13 wherein at least one bit from the predetermined plurality of most significant bits in the single bit sample of said digital representation at said output of the analog-to-digital circuitry is directly connected to an input of said adjustable gain control circuitry.

21. The receiver of claim 13 wherein said analog-to-digital circuitry comprises two analog-to-digital circuits, one of said analog-to-digital circuits having an output directly connected to an input of said adjustable gain control circuitry, whereby both sensitivity and interference tests may be conducted, wherein the gain is connected directly to the digital representation signal at an output of only one of the two analog-to-digital circuits.

22. The receiver of claim 13 wherein said gain is operable to be adjusted by the first amount using the output of the analog-to-digital circuitry without intervention from the digital processing circuitry if the output of the analog-to-digital circuitry is close to saturation over the first saturation threshold.

23. The receiver of claim 13 wherein the both first and second amounts represent a decrease in the gain.

24. The receiver of claim 13 wherein the gain is operable to be adjusted by a third amount responsive to a second set of bits selected from the predetermined plurality of most significant bits in the single bit sample of the digital representation signal, the second set of bits indicating that the output of the analog-to-digital circuitry has fallen below a third saturation threshold.