Switch/network adapter port coupling a reconfigurable processing element to one or more microprocessors for use with interleaved memory controllers

• US 7,565,461 B2
• Filed: 08/15/2005
• Issued: 07/21/2009
• Est. Priority Date: 12/17/1997
• Status: Expired due to Fees

• Current Assignee: FG SRC LLC (Freeman Capital Partners LP)
• Original Assignee: SRC Computers, Inc.
• Inventors: Seeman, Thomas R., Huppenthal, Jon M., Burton, Lee A.
• Primary Examiner(s): Sorrell; Eron J
• Application Number:
  US11/203,983
• Publication Number:
  US 20050283546A1
• Time in Patent Office: 1,436 Days
• Field of Search: None
• US Class Current: 710/22
• CPC Class Codes: G06F 13/1652 in a multiprocessor architecture interprocessor communication using common memory G06F15/167
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices

Abstract

A switch/network adapter port (“SNAP™”) in a dual in-line memory module (“DIMM”) or Rambus™ in-line memory module (“RIMM”) format for clustered computers employing multi-adaptive processor (“MAP®”, both trademarks of SRC Computers, Inc.) elements for use with interleaved memory controllers. Particularly disclosed is a microprocessor based computer system utilizing either a DIMM or RIMM physical format adapter port coupled to a reconfigurable processor element for the purpose of implementing a connection to an external switch, network, or other device. In a particular embodiment, connections may be provided to either the PCI, accelerated graphics port (“AGP”) or system maintenance (“SM”) bus for purposes of passing control information to the host microprocessor or other control chips. The field programmable gate array (“FPGA”) based processing elements have the capability to alter data passing through it to and from an external interconnect fabric or device.

Claims

1. A computer system comprising:

at least one processor including memory mapped registers mapped into the address space of the at least one processor;

a controller for coupling said at least one processor to a control block and a memory bus;

a plurality of memory module slots coupled to said memory bus;

an adapter port associated with a subset of said plurality of memory module slots forming a data path between the adapter port and the memory bus wherein the data path is capable of communicating data at memory bus speeds; and

a processor element including memory mapped registers mapped into the address space of the processor element coupled to said adapter port,

wherein polling of the memory mapped registers mapped into the address space of the processor element by the at least one processor provides a direct low latency communication link via the memory bus and the controller between the processor and the processor element for communicating DMA requests wherein the direct low latency communication link is capable of communicating at memory bus speeds.

2. The computer system of claim 1 wherein said controller comprises an interleaved memory controller.

3. The computer system of claim 1 wherein said plurality of memory module slots comprise DIMM memory module slots.

4. The computer system of claim 3 wherein said adapter port comprises a DIMM physical format for retention within one of said DIMM memory module slots.

5. The computer system of claim 1 wherein said plurality of memory module slots comprise in-line memory module serial interface memory module slots.

6. The computer system of claim 5 wherein said adapter port comprises a in-line memory module serial interface physical format for retention within one of said in-line memory module serial interface memory module slots.

7. The computer system of claim 1 wherein said control block provides control information to said adapter port.

8. The computer system of claim 1 wherein said adapter port comprises:

a memory bus data multiplexer adapted to receive data information from said memory bus.

9. The computer system of claim 8 wherein said adapter port further comprises:

an address and command decoder adapted to receive address information from said memory bus.

10. The computer system of claim 9 further comprising:

a command formatter coupling said address and command decoder to said processor element.

11. The computer system of claim 8 wherein said adapter port further comprises:

a write buffer for coupling said data information received from said memory bus to said processor element; and

a read buffer for coupling data provided by said processor element to said memory bus.

12. The computer system of claim 11 further comprising:

a packetizer for coupling said write buffer to said processor element; and

a depacketizer for coupling said processor element to said read buffer.

13. The computer system of claim 8 further comprising:

a plurality of registers coupled to said memory bus data multiplexer.

14. The computer system of claim 13 wherein said plurality of registers comprise configuration registers.

15. The computer system of claim 13 wherein said plurality of registers comprise status registers.

16. The computer system of claim 1 wherein said processor element comprises a reconfigurable processor element.

17. The computer system of claim 1 wherein said processor element is operative to alter data received from said controller on said memory bus.

18. The computer system of claim 1 wherein said processor element is operative to alter data received from an external source prior to placing altered data on said memory bus.

19. The computer system of claim 1 wherein said processor element comprises:

a processor element control block coupled to said adapter port.

20. The computer system of claim 19 wherein said processor element further comprises:

at least one field programmable gate array configurable to perform an identified algorithm on and operand provided thereto by said adapter port.

21. The computer system of claim 20 further comprising:

a dual-ported memory block coupling the processor element control block coupled to said adapter port to said at least one field programmable gate array.

22. The computer system of claim 1 wherein said processor element comprises:

a chain port for coupling said processor element to another processor element.

23. The computer system of claim 19 wherein said processor element further comprises:

a read only memory associated with said control block for providing configuration information thereto.

24. A method of operating a computer system comprising:

providing at least one processor including memory mapped registers mapped into the address space of the at least one processor;

coupling said at least one processor to a control block and a memory bus;

providing a plurality of memory module slots coupled to said memory bus;

providing an adapter port associated with a subset of said plurality of memory module slots forming a data path between the adapter port and the memory bus wherein the data path is capable of communicating data at memory bus speeds;

providing a processor element including memory mapped registers mapped into the address space of the processor element coupled to said adapter port; and

polling the memory mapped registers mapped into the address space of the processor element by the at least one processor to provide a direct low latency communication link via the memory bus and the controller between the processor and the processor element for communicating DMA requests wherein the direct low latency communication link is capable of communicating at memory bus speeds.