Method and software for store multiplex operation

• US 7,565,515 B2
• Filed: 01/16/2004
• Issued: 07/21/2009
• Est. Priority Date: 08/16/1995
• Status: Expired due to Fees

• Current Assignee: Microunity Systems Engineering Incorporated
• Original Assignee: Microunity Systems Engineering Incorporated
• Inventors: Moussouris, John, Hansen, Craig
• Primary Examiner(s): Coleman; Eric
• Application Number:
  US10/757,866
• Publication Number:
  US 20040205325A1
• Time in Patent Office: 2,013 Days
• Field of Search: 712/224, 712/220, 712/222
• US Class Current: 712/224
• CPC Class Codes: G06F 15/7832 on one IC chip (single chip microprocessors)
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30018 Bit or string instructions
• CPC Class Codes: G06F 9/30025 Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion
• CPC Class Codes: G06F 9/30029 Logical and Boolean instructions, e.g. XOR, NOT
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/30054 Unconditional branch instructions
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/30109 having multiple operands in a single register
• CPC Class Codes: G06F 9/30112 comprising data of variable length
• CPC Class Codes: G06F 9/3012 Organisation of register space, e.g. banked or distributed register file
• CPC Class Codes: G06F 9/30123 according to context, e.g. thread buffers
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/3016 Decoding the operand specifier, e.g. specifier format
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants
• CPC Class Codes: G06F 9/3816 Instruction alignment, e.g. cache line crossing
• CPC Class Codes: G06F 9/3824 : Operand accessing
• CPC Class Codes: G06F 9/383 : Operand prefetching cache prefetching G06F12/0862
• CPC Class Codes: G06F 9/3851 : from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3861 : Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00
• CPC Class Codes: G06F 9/3873 : Variable length pipelines, e.g. elastic pipeline
• CPC Class Codes: G06F 9/3885 : using a plurality of independent parallel functional units

Abstract

A system and software for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions specifying both a mask and a register containing data, the mask comprising fields that each correspond to a field of the data contained in the register, the execution unit is operable to detect some of the fields of the mask as having a predetermined value and identifying corresponding fields of the data contained in the register as write-enabled data fields; and cause the write-enabled data fields to be written to a specified memory location.

Claims

1. A method for processing data using a programmable processor comprising:

decoding a single instruction for writing data to memory based on a mask and data contained in at least one register, the mask consisting of N independently selectable mask bits, N being an integer multiple of eight, each of the mask bits corresponding to a data bit contained in the at least one register, each of the mask bits being independently selectable as either a write-enabled mask bit or a write-disabled mask bit;

detecting some of the mask bits of the mask as being selected as write-enabled mask bits to identify corresponding data bits of the data contained in the at least one register as write-enabled data bits; and

writing the write-enabled data bits to a specified memory location.

2. The method of claim 1 wherein the writing step further comprises reading an unaltered field of data from the specified memory location and writing the unaltered field of data along with the write-enabled data bits to the specified memory location.

3. The method of claim 1 wherein the mask is contained in a specified register.

4. The method of claim 1 wherein the memory location is specified by a register.

5. The method of claim 1 wherein the specified memory location comprises a section of memory having a specific width and beginning at a specific memory address.

6. The method of claim 1 wherein each write-enabled mask bit is indicated as a logic 1.

7. The method of claim 1 further comprising:

decoding a second single instruction specifying a register containing a first plurality of floating-point operands and another register containing a second plurality of floating-point operands;

multiplying the first plurality of floating-point operands by the second plurality of floating-point operands to produce a plurality of products;

and providing the plurality of products to partitioned fields of a result register as a catenated result.

8. A computer-readable storage medium having stored therein a plurality of instructions that cause a programmable processor to perform data operations:

at least some of the instructions including a single instruction for selectively storing data, the single instruction capable of instructing the programmable processor to perform operations comprising;

decoding the single instruction to obtain a mask and data contained in at least one register, the mask consisting of N independently selectable mask bits, N being an integer multiple of eight, each of the mask bits corresponding to a data bit contained in the at least one register, each of the mask bits being independently selectable as either a write-enabled mask bit or a write-disabled mask bit;

detecting some of the mask bits of the mask as being selected as write-enabled mask bits to identify corresponding data bits of the data contained in the at least one register as write-enabled data bits; and

writing the write-enabled data bits to a specified memory location.

9. The computer-readable storage medium of claim 8 wherein the writing step further comprises reading an unaltered field of data from the specified memory location and writing the unaltered field of data along with the write-enabled data bits to the specified memory location.

10. The computer-readable storage medium of claim 8 wherein the mask is contained in a specified register.

11. The computer-readable storage medium of claim 8 wherein the memory location is specified by a register.

12. The computer-readable storage medium of claim 8 wherein the specified memory location comprises a section of memory having a specific width and beginning at a specific memory address.

13. The computer-readable storage medium of claim 8 wherein each write-enabled mask bit is indicated as a logic 1.

14. The computer-readable storage medium of claim 8 wherein at least some of the instructions further include a group floating-point multiply instruction for multiplying floating-point data in the programmable processor, the group floating-point multiply instruction capable of instructing the programmable processor to perform operations comprising:

decoding the group floating-point multiply instruction specifying a register containing a first plurality of floating-point operands and another register containing a second plurality of floating-point operands;

multiplying the first plurality of floating-point operands by the second plurality of floating-point operands to produce a plurality of products; and

providing the plurality of products to partitioned fields of a result register as a catenated result.

15. A method for processing data in a programmable processor, the method comprising:

decoding a single instruction for performing a bitwise insert operation on data in at least one register in a register file within the programmable processor, the bitwise insert operation operating on a first operand and a second operand stored in the at least one register in the register file, the second operand consisting of N independently selectable bits, N being an integer multiple of eight, wherein each bit in the second operand is independently selectable as either having a first predetermined value or a second predetermined value; and

for each bit in the first operand, the bitwise insert operation inserting the bit into a corresponding bit position in a destination value if a corresponding bit in the second operand has the first predetermined value.

16. The method of claim 15 wherein the first predetermined value is a logic 1.

17. The method of claim 15 wherein for each bit in the first operand, a corresponding bit position in the destination value is maintained as unchanged if a corresponding bit in the second operand has a the second predetermined value.

18. The method of claim 17 wherein the second predetermined value is a logic 0.

19. The method of claim 15 further comprising a step of storing the destination value into memory.

20. The method of claim 15 wherein each of the first and second operands has a width of 64 bits.

21. The method of claim 15 further comprising a step of executing a plurality of different group floating-point arithmetic operations that arithmetically operate on multiple floating-point operands stored in partitioned fields of registers in the register file to produce a catenated result that is returned to a register in the register file, wherein the catenated result comprises a plurality of individual floating-point results.

22. A computer-readable storage medium having stored therein a plurality of instructions that cause a programmable processor to perform operations on data in the programmable processor, the plurality of instructions comprising:

an instruction that causes the processor to perform a bitwise insert operation on data in at least one register in a register file within the programmable processor, the bitwise insert operation operating on a first operand and a second operand stored in the at least one register in the register file, the second operand consisting of N independently selectable bits, N being an integer multiple of eight, wherein each bit in the second operand is independently selectable as either having a first predetermined value or a second predetermined value; and

wherein for each bit in the first operand, the bitwise insert operation inserts the bit into a corresponding bit position in a destination value if a corresponding bit in the second operand has the first predetermined value.

23. The computer-readable storage medium of claim 22 wherein the first predetermined value is a logic 1.

24. The computer-readable storage medium of claim 22 wherein for each bit in the first operand, a corresponding bit position in the destination value is maintained as unchanged if a corresponding bit in the second operand has the second predetermined value.

25. The computer-readable storage medium of claim 24 wherein the second predetermined value is a logic 0.

26. The computer-readable storage medium of claim 22 wherein the destination value is stored into memory.

27. The computer-readable storage medium of claim 22 wherein each of the first and second operands has a width of 64 bits.

28. The computer-readable storage medium of claim 22 wherein the plurality of instructions further comprises a plurality of different group floating-point arithmetic operations that arithmetically operate on multiple floating-point operands stored in partitioned fields of registers in the register file to produce a catenated result that is returned to a register in the register file, wherein the catenated result comprises a plurality of individual floating-point results.