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Apparatus and method for memory bit-swapping-within-address-range circuit

  • US 7,565,593 B2
  • Filed: 11/10/2006
  • Issued: 07/21/2009
  • Est. Priority Date: 05/20/2003
  • Status: Expired due to Fees
First Claim
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1. An information-processing apparatus comprising:

  • a first memory having a plurality of addressed locations, each location holding a plurality of bits; and

    a first control circuit, wherein the first control circuit includes;

    a first memory controller coupled to the first memory, the memory controller including;

    a read-bit-swap circuit coupled to receive data from the first memory, the read-bit-swap circuit including a plurality of two-input one-output multiplexers, wherein each read bit is coupled to one input on each of two non-adjacent multiplexers;

    a write-data bit-swap circuit coupled to transmit data to the first memory, the write-bit-swap circuit including a plurality of two-input one-output multiplexers, wherein each bit to be written is coupled to one input on each of two non-adjacent multiplexers; and

    a swap-controller circuit operatively coupled to the read-bit-swap circuit and to the write-data bit-swap circuit to selectively choose one or more spare bits in place of a corresponding number of other bits.

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