Apparatus and method for memory bit-swapping-within-address-range circuit
First Claim
1. An information-processing apparatus comprising:
- a first memory having a plurality of addressed locations, each location holding a plurality of bits; and
a first control circuit, wherein the first control circuit includes;
a first memory controller coupled to the first memory, the memory controller including;
a read-bit-swap circuit coupled to receive data from the first memory, the read-bit-swap circuit including a plurality of two-input one-output multiplexers, wherein each read bit is coupled to one input on each of two non-adjacent multiplexers;
a write-data bit-swap circuit coupled to transmit data to the first memory, the write-bit-swap circuit including a plurality of two-input one-output multiplexers, wherein each bit to be written is coupled to one input on each of two non-adjacent multiplexers; and
a swap-controller circuit operatively coupled to the read-bit-swap circuit and to the write-data bit-swap circuit to selectively choose one or more spare bits in place of a corresponding number of other bits.
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Abstract
A memory controller and method that provide a read-refresh (also called “distributed-refresh”) mode of operation, in which every row of memory is read within the refresh-rate requirements of the memory parts, with data from different columns within the rows being read on subsequent read-refresh cycles until all rows for each and every column address have been read, scrubbing errors if found, thus providing a scrubbing function that is integrated into the read-refresh operation, rather than being an independent operation. For scrubbing, an atomic read-correct-write operation is scheduled. A variable-priority, variable-timing refresh interval is described. An integrated card self-tester and/or card reciprocal-tester is described. A memory bit-swapping-within-address-range circuit, and a method and apparatus for bit swapping on the fly and testing are described.
84 Citations
48 Claims
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1. An information-processing apparatus comprising:
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a first memory having a plurality of addressed locations, each location holding a plurality of bits; and a first control circuit, wherein the first control circuit includes; a first memory controller coupled to the first memory, the memory controller including; a read-bit-swap circuit coupled to receive data from the first memory, the read-bit-swap circuit including a plurality of two-input one-output multiplexers, wherein each read bit is coupled to one input on each of two non-adjacent multiplexers; a write-data bit-swap circuit coupled to transmit data to the first memory, the write-bit-swap circuit including a plurality of two-input one-output multiplexers, wherein each bit to be written is coupled to one input on each of two non-adjacent multiplexers; and a swap-controller circuit operatively coupled to the read-bit-swap circuit and to the write-data bit-swap circuit to selectively choose one or more spare bits in place of a corresponding number of other bits. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. An information-processing method comprising:
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receiving a first memory request that specifies a first address; detecting whether the first address of the first memory request is within a specified range of addresses; and if the first memory request is for one or more write operations; shifting a first subset of bit positions a plurality of bit positions in a first direction for first data of each write operation address being detected as within the specified range, and writing the bit-swapped first data to the memory; and if the first memory request is for one or more read operations; reading second data from the memory, and shifting a second subset of bit positions a plurality of bit positions in a second direction opposite the first direction for each read operation address being detected as within the specified range. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34)
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35. An information-processing apparatus comprising:
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a first memory having a plurality of addressed locations, each location holding a plurality of bits; and a first control circuit, wherein the first control circuit includes; a first memory controller coupled to the first memory, the memory controller including; means for shifting a first subset of bit positions a plurality of bit positions in a first direction for each write-operation address being detected as within the specified range, and for writing the bit-swapped first data to the memory; and means for reading the first data to the memory, and for shifting a second subset of bit positions a plurality of bit positions in a second direction opposite the first direction for each read-operation address being detected as within the specified range. - View Dependent Claims (36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48)
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Specification