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SOI device with reduced drain induced barrier lowering

  • US 7,566,600 B2
  • Filed: 09/28/2006
  • Issued: 07/28/2009
  • Est. Priority Date: 08/31/2000
  • Status: Expired due to Fees
First Claim
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1. A method for fabricating an integrated circuit, comprising:

  • providing a substrate having a semiconductor region overlying a completely formed insulator;

    subsequently initiating implanting the completely formed insulator with electrical dopant to form an N-type dopant diffusion source, wherein the insulator is completely formed before forming the N-type diffusion source;

    initiating implanting the completely formed insulator with electrical dopant to form a P-type dopant diffusion source after providing the substrate, the p-type dopant diffusion source separated from the n-type dopant diffusion source; and

    diffusing N-type and P-type electrical dopant from the insulator out into the semiconductor region, a concentration of each of the N-type and P-type electrical dopants in the seminconductor region defining a retrograde dopant profile after diffusing.

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