SOI device with reduced drain induced barrier lowering
First Claim
1. A method for fabricating an integrated circuit, comprising:
- providing a substrate having a semiconductor region overlying a completely formed insulator;
subsequently initiating implanting the completely formed insulator with electrical dopant to form an N-type dopant diffusion source, wherein the insulator is completely formed before forming the N-type diffusion source;
initiating implanting the completely formed insulator with electrical dopant to form a P-type dopant diffusion source after providing the substrate, the p-type dopant diffusion source separated from the n-type dopant diffusion source; and
diffusing N-type and P-type electrical dopant from the insulator out into the semiconductor region, a concentration of each of the N-type and P-type electrical dopants in the seminconductor region defining a retrograde dopant profile after diffusing.
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Accused Products
Abstract
A CMOS device formed with a Silicon On Insulator (SOI) technology with reduced Drain Induced Barrier Lowering (DIBL) characteristics and a method for producing the same. The method involves a high energy, high dose implant of boron and phosphorus through the p- and n-wells, into the insulator layer, thereby creating a borophosphosilicate glass (BPSG) structure within the insulation layer underlying the p- and n-wells of the SOI wafer. Backend high temperature processing steps induce diffusion of the boron and phosphorus contained in the BPSG into the p- and n-wells, thereby forming a retrograde dopant profile in the wells. The retrograde dopant profile reduces DIBL and also provides recombination centers adjacent the insulator layer and the active layer to thereby reduce floating body effects for the CMOS device.
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Citations
23 Claims
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1. A method for fabricating an integrated circuit, comprising:
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providing a substrate having a semiconductor region overlying a completely formed insulator; subsequently initiating implanting the completely formed insulator with electrical dopant to form an N-type dopant diffusion source, wherein the insulator is completely formed before forming the N-type diffusion source; initiating implanting the completely formed insulator with electrical dopant to form a P-type dopant diffusion source after providing the substrate, the p-type dopant diffusion source separated from the n-type dopant diffusion source; and diffusing N-type and P-type electrical dopant from the insulator out into the semiconductor region, a concentration of each of the N-type and P-type electrical dopants in the seminconductor region defining a retrograde dopant profile after diffusing. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method for semiconductor processing, comprising:
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providing a plurality of separated dopant diffusion sources in an insulator, wherein some of the dopant diffusion sources comprise a different type of electrical dopant from others of the dopant diffusion sources; providing a silicon region above the insulator, and establishing a retrograde doping profile for each of the different types of electrical dopants in desired parts of the silicon region by diffusion of the different types of electrical dopants out of the diffusion sources and into the silicon region. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23)
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Specification