SOI device with reduced drain induced barrier lowering

• US 7,566,600 B2
• Filed: 09/28/2006
• Issued: 07/28/2009
• Est. Priority Date: 08/31/2000
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Mouli, Chandra V.
• Primary Examiner(s): Quach; Tuan N.
• Application Number:
  US11/529,899
• Publication Number:
  US 20070026652A1
• Time in Patent Office: 1,034 Days
• Field of Search: 438/149, 438/154, 438/217, 438/459, 438/194, 438/558, 438/563, 257/E21.149
• US Class Current: 438/154
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/26533 of electrically inactive species in silicon to make buried insulating layers
• CPC Class Codes: H01L 21/2658 of a molecular ion, e.g. decaborane
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A CMOS device formed with a Silicon On Insulator (SOI) technology with reduced Drain Induced Barrier Lowering (DIBL) characteristics and a method for producing the same. The method involves a high energy, high dose implant of boron and phosphorus through the p- and n-wells, into the insulator layer, thereby creating a borophosphosilicate glass (BPSG) structure within the insulation layer underlying the p- and n-wells of the SOI wafer. Backend high temperature processing steps induce diffusion of the boron and phosphorus contained in the BPSG into the p- and n-wells, thereby forming a retrograde dopant profile in the wells. The retrograde dopant profile reduces DIBL and also provides recombination centers adjacent the insulator layer and the active layer to thereby reduce floating body effects for the CMOS device.

Claims

1. A method for fabricating an integrated circuit, comprising:

providing a substrate having a semiconductor region overlying a completely formed insulator;

subsequently initiating implanting the completely formed insulator with electrical dopant to form an N-type dopant diffusion source, wherein the insulator is completely formed before forming the N-type diffusion source;

initiating implanting the completely formed insulator with electrical dopant to form a P-type dopant diffusion source after providing the substrate, the p-type dopant diffusion source separated from the n-type dopant diffusion source; and

diffusing N-type and P-type electrical dopant from the insulator out into the semiconductor region, a concentration of each of the N-type and P-type electrical dopants in the seminconductor region defining a retrograde dopant profile after diffusing.

2. The method of claim 1, wherein the p-type dopant comprises phosphorus and the n-type dopant comprises boron.

3. The method of claim 2, wherein doping forms borophosphosilicate glass (BPSG) within the insulator.

4. The method of claim 1, wherein diffusing comprises exposing the substrate to an elevated temperature.

5. The method of claim 4, wherein exposing the substrate to the elevated temperature comprises forming a passivation layer over the insulator.

6. The method of claim 1, wherein the concentration of the electrical dopant in the insulator is at least about 10²⁰/cm³.

7. The method of claim 6, wherein the concentration of the electrical dopant in the seminconductor region is at least about 9×

10¹⁷/cm³ after diffusing.

8. The method of claim 1, wherein the substrate is a Separation by IMplanted OXygen (SIMOX) wafer.

9. The method of claim 1, wherein the insulator comprises a buried silicon dioxide layer.

10. The method of claim 1, wherein the semiconductor region is an epitaxial silicon layer.

11. A method for semiconductor processing, comprising:

providing a plurality of separated dopant diffusion sources in an insulator, wherein some of the dopant diffusion sources comprise a different type of electrical dopant from others of the dopant diffusion sources;

providing a silicon region above the insulator, and

establishing a retrograde doping profile for each of the different types of electrical dopants in desired parts of the silicon region by diffusion of the different types of electrical dopants out of the diffusion sources and into the silicon region.

12. The method of claim 11, wherein establishing the retrograde doping profile comprises forming electrical devices over the plurality of dopant diffusion sources.

13. The method of claim 12, wherein forming electrical devices over the plurality of dopant diffusion sources comprises exposing the dopant diffusion sources to an elevated temperature, wherein the elevated temperature causes diffusion of the electrical dopants out of the diffusion source.

14. The method of claim 12, wherein forming electrical devices comprises depositing a passivation layer over the silicon region.

15. The method of claim 14, wherein the passivation layer comprises an oxide, borophosphosilicate glass or polysilicon.

16. The method of claim 12, wherein forming electrical devices forms transistors.

17. The method of claim 16, wherein forming electrical devices forms complementary transistor devices.

18. The method of claim 17, wherein forming transistor devices comprises forming at least one each of a NMOS and a PMOS device.

19. The method of claim 12, further comprising adjusting threshold voltages of the transistor devices.

20. The method of claim 19, wherein adjusting threshold voltages comprises implanting an other dopant into the semiconductor region.

21. The method of claim 20, wherein implanting the other dopant comprises implantation using BF₂.

22. The method of claim 20, wherein the other dopant comprises arsenic.

23. The method of claim 11, wherein providing dopant diffusion sources comprises implanting electrical dopants substantially adjacent an interface between the insulator and the silicon region.