DRAM including a vertical surround gate transistor

• US 7,566,620 B2
• Filed: 07/31/2006
• Issued: 07/28/2009
• Est. Priority Date: 07/25/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Abbott, Todd R.
• Primary Examiner(s): Smith; Zandra
• Assistant Examiner(s): Patton; Paul E
• Application Number:
  US11/461,246
• Publication Number:
  US 20070018223A1
• Time in Patent Office: 1,093 Days
• Field of Search: 257/67, 257/296, 257/298, 257/302, 257/326, 257/908, 257/E27.084, 257/E27.088, 257/E29.13, 257/E29.131, 438/268, 438/270
• US Class Current: 438/268
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate
• CPC Class Codes: H10B 12/485 Bit line contacts
• CPC Class Codes: H10B 12/488 Word lines

Abstract

DRAM memory cells having a feature size of less than about 4F2 include vertical surround gate transistors that are configured to reduce any short channel effect on the reduced size memory cells. In addition, the memory cells may advantageously include reduced resistance word line contacts and reduced resistance bit line contacts, which may increase a speed of the memory device due to the reduced resistance of the word line and bit line contacts.

Claims

1. A method of forming a vertical memory cell, the method comprising:

forming a vertical memory cell comprising;

a source,

a drain,

a polysilicon surround gate to extend in a first generally vertically extending direction, and

a generally vertically extending channel region, wherein the source is arranged at an upper end of the vertically extending channel region and wherein the drain is arranged at an opposite lower end of the vertically extending channel region;

depositing a dielectric to cover a horizontal upper surface of the polysilicon surround gate;

forming a trench extending along the surround gate so as to expose a vertical surface of the surround gate;

depositing a thin metal on the exposed vertical surface of at least the polysilicon surround gate while the horizontal upper surface of the polysilicon surround gate remains covered by the dielectric;

exposing the thin metal to heat that is sufficiently high to react at least a portion of the thin metal with at least a portion of the polysilicon gate in order to form a silicided gate extending along a vertical length of the formerly exposed vertical surface of the polysilicon surround gate;

forming a spacer arranged to cover at least the silicided gate contact; and

forming a second separate generally vertical conductive path extending from a drain contact upwards to above the surround gate, wherein the drain contact is arranged adjacent the lower end of the vertically extending channel region.

2. The method of claim 1, wherein the thin metal comprises Cobalt.

3. The method of claim 1, wherein the thin metal comprises Nickel.

4. The method of claim 1, wherein the thin metal comprises Titanium.

5. The method of claim 1, wherein the thin metal comprises a layer of either Cobalt or Nickel and a layer of either Titanium or Titanium Nitride.

6. The method of claim 1, further comprising siliciding at least a portion of the drain such that the drain contact is at least partially silicided.

7. The method of claim 1, wherein the polysilicon surround gate comprises a word line contact.

8. The method of claim 1, wherein the memory cell comprises a DRAM cell.

9. The method of claim 1, further comprising forming a capacitor in contact with the source.

19. The method of claim 1, further comprising forming a bit line in contact with the separate second generally vertical conductive path such that the bit line is arranged at an elevation above the surround gate.

20. The method of claim 19, further comprising forming a word line such that the word line and the bit line are non-orthogonal.

10. A vertical memory cell comprising:

a source region;

a drain region;

a polysilicon surround gate extending generally vertically between the source region and drain region;

a channel region extending generally vertically between the source region and the drain region wherein the source region is arranged at an upper end of the vertically extending channel region and wherein the drain region is arranged at an opposite lower end of the vertically extending channel region;

a vertically extending silicided surround gate contact arranged adjacent the polysilicon surround gate wherein the polysilicon surround gate and the silicided surround gate contact extend along a vertical length of the channel region;

an insulating sidewall spacer arranged to cover a vertical outer surface of the silicided gate contact; and

a separate second conductive path extending generally vertically from a silicided drain contact over the drain region to above the polysilicon surround gates and the spacer and wherein the drain contact is arranged adjacent the lower end of the vertically extending channel region, the second conductive path insulated from the silicided surround gate contact by the insulating sidewall spacer.

11. A method of forming a memory device comprising a plurality of vertical memory cells, the method comprising:

forming a plurality of vertical memory cells each comprising a polysilicon surround gate vertically extending over a channel region, a source arranged generally at an upper end of the channel region, and a drain arranged generally at an opposite lower end of the channel region;

depositing dielectric to cover upper surfaces of the polysilicon surround gates;

forming trenches to expose vertical surfaces of the polysilicon surround gates;

depositing a thin metal on the exposed vertical surfaces of the polysilicon surround gate of each memory cell;

exposing the thin metal to heat that is sufficiently high to react at least a portion of the thin metal with at least a portion of the polysilicon gate in order to form a silicided gate contact adjacent and extending across an entire vertical length of the polysilicon surround gate in each of the memory cells;

forming sidewall spacers arranged to cover at least the silicided gate contacts; and

forming second separate generally vertical conductive paths extending from respective drain contacts upwards to above the respective surround gate, wherein the drain contacts are arranged adjacent the lower end of the respective vertically extending channel region and wherein the second generally vertical conductive paths are isolated from the silicided gate contacts by the sidewall spacers.

12. The method of claim 11, further comprising siliciding at least a portion of the drains of each of the memory cells such that the drain contacts in each memory cell are at least partially silicided.

13. The method of claim 12, wherein bit lines of the memory device are electrically connected to first subsets of the silicided drain contacts via respective separate second vertical conductive paths.

14. The method of claim 11, wherein a word line of the memory device comprises a second subset of the polysilicon surround gates.

15. The method of claim 11, wherein the thin metal comprises material selected from the group comprising Tungsten, Nickel, and Cobalt.

16. The method of claim 11, further comprising depositing a second thin metal on the thin metal prior to exposing the thin metal to heat.

17. The method of claim 16, wherein the second thin metal comprises material selected from the group comprising Titanium and Titanium Nitride.

18. The method of claim 11, wherein the memory device comprises a DRAM.

21. The method of claim 11, further comprising forming a plurality of word lines and a plurality of bit lines such that the word lines and the bit lines are non-orthogonal.

22. The method of claim 11, further comprising forming bit lines in contact with respective separate second generally vertical conductive paths such that the bit lines are arranged at an elevation above the respective surround gates.