Method for chip singulation
First Claim
1. A method of singulating at least one chip from a stack of layers, the stack comprising a front end of line upon a substrate layer, the substrate layer having a first surface and a second surface, the front end of line being positioned on top of the first surface, and a back end of line on top of the front end of line, the method comprising:
- etching singulating trenches through the back end of line, through the front end of line and at least partially through the substrate layer of the stack;
depositing a passivation layer on the stack provided with the etched singulating trenches, such that sidewalls of the trenches are at least partially passivated; and
releasing the at least one chip from the stack of layers by reducing the thickness of the substrate layer from the second surface onwards to the bottom of the etched singulating trenches until the at least one chip is released from the stack.
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Accused Products
Abstract
The present invention is related to a method for singulating chips from a stack of layers, such as the layers on a wafer or substrate. The stack of layers includes a front end of line (FEOL) layer upon the substrate layer, with the substrate layer having a first surface and a second surface. The FEOL is positioned on top of the first surface, and a back end of line (BEOL) layer is positioned on top of the FEOL. The method includes etching singulating trenches through the BEOL, through the FEOL and at least partially through the substrate layer, depositing a passivation layer on the stack provided with singulating trenches, whereby the sidewalls of the etched singulating trenches are at least partially passivated. Dicing, such as blade dicing, laser dicing or trench etch dicing is performed, releasing the chip from the stack of layers.
36 Citations
30 Claims
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1. A method of singulating at least one chip from a stack of layers, the stack comprising a front end of line upon a substrate layer, the substrate layer having a first surface and a second surface, the front end of line being positioned on top of the first surface, and a back end of line on top of the front end of line, the method comprising:
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etching singulating trenches through the back end of line, through the front end of line and at least partially through the substrate layer of the stack; depositing a passivation layer on the stack provided with the etched singulating trenches, such that sidewalls of the trenches are at least partially passivated; and releasing the at least one chip from the stack of layers by reducing the thickness of the substrate layer from the second surface onwards to the bottom of the etched singulating trenches until the at least one chip is released from the stack. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 30)
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14. A method of singulating at least one chip from a stack of layers, the stack comprising a front end of line upon a substrate layer, the substrate layer having a first surface and a second surface, the front end of line being positioned on top of the first surface, and a back end of line on top of the front end of line, the method comprising:
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positioning metal dummies in the back end of line, wherein the metal dummies are positioned outside a chip area and outside an exclusion zone, the exclusion zone surrounding the at least one chip; and etching singulating trenches through the back end of line, through the front end of line and at least partially through the substrate layer of the stack, wherein the etching is done in the exclusion zone and the singulating trenches surround the at least one chip. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29)
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Specification