Multi-stacked package and method of manufacturing the same

• US 7,566,961 B2
• Filed: 12/12/2006
• Issued: 07/28/2009
• Est. Priority Date: 12/19/2005
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Cho, Yeoung-Jun
• Primary Examiner(s): CLARK, SHEILA V
• Application Number:
  US11/609,840
• Publication Number:
  US 20070138631A1
• Time in Patent Office: 959 Days
• Field of Search: 257/686, 257/777, 257/778, 438/107, 438/108, 438/109
• US Class Current: 257/686
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/15192 Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/3511 Warping
• CPC Class Codes: H05K 2201/0379 Stacked conductors
• CPC Class Codes: H05K 2201/10515 Stacked components
• CPC Class Codes: H05K 2201/10666 Plated through-hole for surface mounting on PCB
• CPC Class Codes: H05K 2201/10734 Ball grid array [BGA]; Bump grid array
• CPC Class Codes: H05K 2203/0455 PTH for surface mount device [SMD], e.g. wherein solder flows through the PTH during mounting
• CPC Class Codes: H05K 3/3436 having an array of bottom contacts, e.g. pad grid array or ball grid array components
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product

Abstract

A multi-stacked package includes a first package, a second package and a combining member. The second package supports the first package, and is electrically connected to the first package and has at least one joint hole. The combining member extends from the first package to below the second package to pass through the joint hole so that the combining member is partially exposed to improve the coherence between the first package and the second package.

Claims

1. A multi-stacked package comprising:

a first package;

a second package supporting the first package, the second package being electrically connected to the first package and having at least one joint hole;

a combining member extending from the first package to below the second package, the combining member disposed to pass through the joint hole so that the combining member is partially exposed below the second package; and

a conductive layer formed on an inner surface of the joint hole and on lower and upper surfaces of the second package near the joint hole,

wherein the first package includes a first substrate secured to the combining member, a first semiconductor chip disposed on the first substrate and first conductive balls disposed beneath the first substrate, and the second package includes a second substrate though which the combining member penetrates, a second semiconductor chip disposed on the second substrate and second conductive balls disposed beneath the second substrate, and

wherein the combining member has a size substantially greater than those of the first and second conductive balls.

2. The multi-stacked package of claim 1, wherein the combining member has a substantially spherical shape.

3. The multi-stacked package of claim 1, wherein a plurality of the joint holes is formed along a peripheral portion of the second substrate.

4. The multi-stacked package of claim 1, wherein the second substrate has a rectangular shape, the second substrate has four joint holes, and one of the joint holes is formed at each of four corners of the second substrate.

5. A method of manufacturing a multi-stacked package, the method comprising:

securing a first semiconductor chip to a first substrate;

forming first conductive balls, which are electrically connected to the first semiconductor chip, beneath the first substrate;

positioning a first package on a second package, the second package including a joint hole;

forming a combining member protruded from the first package to below the second package to pass through the joint hole so that the combining member is partially exposed below the second package; and

heating the combining member and the first conductive balls substantially simultaneously.

6. The method of claim 5, further comprising forming a conductive layer on an inner side of the joint hole and lower and upper surfaces of the second package.

7. The method of claim 5, prior to positioning the first package on the second package, further comprising:

securing a second semiconductor chip to a second substrate having at least one joint hole; and

forming second conductive balls, which are electrically connected to the second semiconductor chip, beneath the second substrate.

8. The method of claim 7, further comprising heating the combining member and the second conductive balls substantially simultaneously.

9. A method of manufacturing a multi-stacked package, the method comprising:

providing a first semiconductor package, the first semiconductor package including at least one joint hole, wherein providing the first semiconductor package includes;

mounting a first semiconductor chip on a first substrate; and

forming first conductive balls on a lower surface of the first substrate, the first conductive balls electrically connected to the first semiconductor chip;

mounting the first semiconductor package on a mounting board, wherein mounting the first semiconductor package on the mounting board comprises Positioning the first semiconductor package on the mounting board and heating the first conductive balls;

forming a combining member in the joint hole such that the combining member physically and electrically connects the first semiconductor package and the mounting board; and

mounting a second semiconductor package on the first semiconductor package such that the combining member physically and electrically connects the second semiconductor package to the first semiconductor package.

10. The method of claim 9, wherein forming the combining member comprises positioning the combining member in the joint hole and heating the combining member.

11. The method of claim 10, wherein the first conductive balls and the combining member are heated substantially simultaneously.

12. The method of claim 9, wherein mounting the second semiconductor package on the first semiconductor package comprises:

mounting a second semiconductor chip on a second substrate;

forming second conductive balls on a lower surface of the second substrate, the second conductive balls electrically connected to the second semiconductor chip;

positioning the second semiconductor package on the first semiconductor package; and

heating the second conductive balls.

13. The method of claim 12, wherein the combining member is heated substantially simultaneously with the second conductive balls.

14. A multi-stacked package, comprising:

a first package;

a second package disposed below the first package such that the first package is mounted on the second package;

a conductive member, the conductive member penetrating through the second package and disposed to contact the first package;

a first solder ball attached to an underside of the first package, the first solder ball connected to the second package; and

a second solder ball attached to an underside of the second package, wherein a surface area of the conductive member in contact with the first package is larger than a surface area of the first solder ball in contact with the first package.

15. The multi-stacked package of claim 14, wherein a diameter of the conductive member is larger than a diameter of the first solder ball.

16. The multi-stacked package of claim 14, wherein the conductive member is also in contact with the second package.