Liquid crystal display driver including test pattern generating circuit

• US 7,567,092 B2
• Filed: 03/28/2007
• Issued: 07/28/2009
• Est. Priority Date: 04/11/2006
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Park, Jee-woo, Kang, Won-sik, Bae, Jong-kon
• Primary Examiner(s): Nguyen; Ha Tran T
• Assistant Examiner(s): Nguyen; Tung X
• Application Number:
  US11/692,562
• Publication Number:
  US 20070236243A1
• Time in Patent Office: 853 Days
• Field of Search: 324/770, 324/765, 324/760, 324/763, 324/158.1, 349 40- 42, 349/38, 349/48, 345/94, 345/100, 345/204
• US Class Current: 324/760.01
• CPC Class Codes: G09G 2320/0693 Calibration of display systems
• CPC Class Codes: G09G 2360/18 Use of a frame buffer in a display terminal, inclusive of the display panel
• CPC Class Codes: G09G 3/006 Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309

Abstract

A liquid crystal display (LCD) driver including a normal mode circuit, a test pattern generating circuit, a selection circuit, and a timing controller. The normal mode circuit generates a normal mode signal related to a normal image data writing operation of an LCD. The test pattern generating circuit generates a test mode signal related to a test image data writing operation of the LCD. The selection circuit selects one of the normal mode signal and the test mode signal. The timing controller includes a memory storing image data that constructs a normal image pattern or a test image pattern displayed on an LCD panel of the LCD in response to an output signal of the selection circuit.

Claims

1. An LCD (liquid crystal display) driver comprising:

a normal mode circuit for generating a normal mode signal related to a normal image data writing operation of an LCD;

a test pattern generating circuit for generating a test mode signal related to a test image data writing operation of the LCD;

a selection circuit for selecting one of the normal mode signal and the test mode signal; and

a timing controller including a memory storing image data that constructs a normal image pattern or a test image pattern for display on an LCD panel of the LCD in response to an output signal of the selection circuit, wherein the displayed test image pattern is used for a visual quality test, and

wherein the test mode signal includes test image data constructing the test image pattern, a test memory selection signal for activating or deactivating the memory a test row address signal and a test column address signal designating a position of the test image data stored in the memory, a delayed test enable signal obtained by delaying a test enable signal for enabling the test pattern generating circuit, and a test write clock signal synchronized with the test memory selection signal, the test row address signal and the test column address signal, wherein the selection circuit is operated in response to the delayed test enable signal.

2. The LCD driver of claim 1, wherein the test pattern generating circuit comprises:

a delay unit for delaying the test enable signal to generate the delayed test enable signal;

a clock generator enabled in response to the test enable signal, wherein the clock generator generates the test write clock signal in response to an oscillator clock signal;

an address generator for generating the test memory selection signal, the test row address signal, and the test column address signal in response to the test write clock signal; and

a test pattern generator including a storage unit storing test image patterns, selecting one of the test image patterns as the test image pattern in response to a test pattern selection signal and RGB data, and outputting the test image data designated by the test row address signal and the test column address signal of the selected test image pattern.

3. The LCD driver of claim 2, wherein the clock generator and the address generator are reset in response to a reset signal.

4. The LCD driver of claim 3, wherein the test enable signal, the reset signal, and the RGB data are input from a CPU through a CPU interface and the test pattern selection signal is input by a user of the LCD driver.

5. The LCD driver of claim 4, further comprising an oscillator generating the oscillator clock signal.

6. The LCD driver of claim 5, wherein the timing controller receives a control signal output from the CPU through the CPU interface and generates a control signal for controlling the LCD driver to drive the LCD panel, and wherein the control signal output from the CPU is a dot clock signal corresponding to a system clock signal.

7. The LCD driver of claim 6, wherein the memory is configured using a graphic RAM.

8. The LCD driver of claim 6, wherein the selection circuit is configured as a multiplexer.

9. The LCD driver of claim 6, wherein the address generator is configured as a counter.

10. The LCD driver of claim 1, further comprising:

a gate driver circuit driving gate lines of the LCD panel in response to a control signal output from the timing controller; and

a source driver circuit driving source lines of the LCD panel in response to image data output from the memory and the control signal output from the timing controller,

wherein the timing controller receives a control signal output from a CPU through a CPU interface and generates the control signal for controlling operation timing of the gate driver circuit and the source driver circuit, and wherein the control signal output from the CPU is a dot clock signal corresponding to a system clock signal.