Rate generator in a video on demand system having multiple constant bit rate data

• US 7,567,589 B2
• Filed: 10/24/2006
• Issued: 07/28/2009
• Est. Priority Date: 04/01/1999
• Status: Active Grant

• Current Assignee: Comcast IP Holdings I LLC (Comcast Corporation)
• Original Assignee: Comcast IP Holdings I LLC (Comcast Corporation)
• Inventors: Caracciolo, Gerald T., Zack, Steven
• Primary Examiner(s): Ngo; Ricky
• Assistant Examiner(s): NG, CHRISTINE Y
• Application Number:
  US11/585,482
• Publication Number:
  US 20070091936A1
• Time in Patent Office: 1,008 Days
• Field of Search: 370/516, 370/517, 370/518, 370/252, 725/87, 725/101
• US Class Current: 370/516
• CPC Class Codes: H04N 21/23439 for generating different versions
• CPC Class Codes: H04N 21/23655 Statistical multiplexing, e.g. by controlling the encoder to alter its bitrate to optimize the bandwidth utilization
• CPC Class Codes: H04N 21/47202 for requesting content on demand, e.g. video on demand
• CPC Class Codes: H04N 7/17309 Transmission or handling of upstream communications

Abstract

A rate generator for generating a plurality of different frequencies that represent video requests in a video on demand (VOD) system. The rate generator comprises a plurality of parallel groups, each group comprising a phase accumulator module having a plurality of phase accumulators, a phase increment model having a plurality of phase increment registers, and an adder, coupled to the phase accumulator module and the phase increment module. The adder sums the phase increment value from the phase from the phase increment module and the output of the phase accumulator module and provides the value back to the phase accumulator module. When the sum reaches a pre-determined value, the adder resets and generates a pulse at a frequency dependent on the phase increment and the sampling frequency. In addition, a method for deriving the rate generator architecture is also provided.

Claims

1. A method for deriving and implementing a rate generator architecture for a selected number of users, the rate generator architecture having a plurality of physical accumulators, each physical accumulator being sequentially operated as a plurality of virtual accumulators, the method comprising:

calculating a number of bits required for each accumulator in the rate generator architecture;

calculating a number of virtual accumulators to sequentially implement for each of the physical accumulators in the rate generator architecture; and

calculating a number of physical accumulators for the rate generator architecture using the calculated number of virtual accumulators and the selected number of users;

generating a number of different clock signals corresponding to the selected number of users in a time-shared manner using the calculated number of physical accumulators.

2. The method of claim 1, wherein the method further comprises the steps of:

providing an adder for each of the physical accumulators; and

providing one phase increment register for each of the physical accumulators.

3. The method of claim 1, wherein calculating the number of bits comprises the steps of:

determining a maximum sampling rate for transmitting data packets;

determining an error frequency associated with a tolerable packet error; and

calculating the number of bits required from the maximum sampling rate and the error frequency.

4. The method of claim 3, wherein determining the maximum sampling rate comprises the steps of:

providing a number of bits per packet;

providing a maximum bit rate;

determining a maximum packet frequency from the maximum bit rate and the number of bits per packet;

selecting a number of samples per packet; and

determining a maximum sampling frequency from the number of samples per packet and the maximum packet frequency.

5. The method of claim 1, wherein calculating the number of virtual accumulators to sequentially implement comprises the steps of:

adjusting the sampling frequency;

selecting a clock frequency; and

calculating the number of bits virtual accumulators to sequentially implement from the adjusted sampling frequency and the clock frequency.

6. The method of claim 1, wherein calculating the number of virtual accumulators to sequentially implement comprises the steps of:

determining a sampling frequency;

selecting a clock frequency; and

calculating the number of virtual accumulators to sequentially implement from the sampling frequency and the clock frequency.

7. The method of claim 6, wherein determining the sampling frequency comprises the steps of:

determining an error frequency associated with a tolerable packet error; and

determining the sampling frequency from the error frequency associated with a tolerable packet error and the number of bits required of each accumulator.

8. The method of claim 1, wherein calculating the number of virtual accumulators to sequentially implement comprises the steps of:

calculating an adjusted sampling frequency;

calculating an updated error frequency from the adjusted sampling frequency and the number of bits required of each accumulator; and

verifying that the updated error frequency is less than or equal to an error frequency associated with a tolerable packet error.

9. The method of claim 8, wherein the adjusted sampling frequency is calculated from a selected clock frequency and said number of virtual accumulators to sequentially implement.

10. The method of claim 1, wherein calculating the number of physical accumulators comprises the step of:

calculating the number of physical accumulators by dividing the selected number of users by the calculated number of virtual accumulators to sequentially implement.

11. An apparatus for deriving a rate generator architecture having a plurality of physical accumulators, each physical accumulator for being sequentially operated as a plurality of virtual accumulators, the rate generator architecture for a selected number of users, the apparatus comprising:

means for calculating a number of bits required of each accumulator;

means for calculating a number of virtual accumulators to sequentially implement for each of the physical accumulators; and

means for calculating a number of physical accumulators for the rate generator architecture using the calculated number of virtual accumulators and the selected number of users.

12. The apparatus of claim 11, further comprising:

means for providing an adder for each of the physical accumulators; and

means for providing one phase increment register for each of the physical accumulators.

13. The apparatus of claim 11, wherein said means for calculating the number of bits comprises:

means for determining a maximum sampling rate for transmitting data packets;

means for determining an error frequency associated with a tolerable packet error; and

means for calculating the numbers of bits required from the maximum sampling rate and the error frequency.

14. The apparatus of claim 13, wherein the means for determining the maximum sampling rate comprises:

means for providing a number of bits per packet;

means for providing a maximum bit rate;

means for determining a maximum packet frequency from the maximum bit rate and the number of bits per packet;

means for selecting a number of samples per packet; and

means for determining a maximum sampling frequency from the number of samples per packet and the maximum packet frequency.

15. The apparatus of claim 11, wherein the means for calculating the number of virtual accumulators to sequentially implement comprises:

means for adjusting the sampling frequency;

means for selecting a clock frequency; and

means for calculating the number of virtual accumulators to sequentially implement from the adjusted sampling frequency and the clock frequency.

16. The apparatus of claim 11, wherein the means for calculating the number of virtual accumulators to sec,uentially implement comprises:

means for determining a sampling frequency;

means for selecting a clock frequency; and

means for calculating the number of virtual accumulators to sequentially implement from the sampling frequency and the clock frequency.

17. The apparatus of claim 16, wherein the means for determining the sampling frequency comprises:

means for determining an error frequency associated with a tolerable packet error; and

means for determining the sampling frequency from the error frequency associated with a tolerable packet error and the number of bits required of each accumulator.

18. The apparatus of claim 11, wherein the means for calculating the number of virtual accumulators to seciuentiallv implement comprises:

means for calculating an adjusted sampling frequency;

means for calculating an updated error frequency from the adjusted sampling frequency and the number of bits required of each accumulator; and

means for verifying that the updated error frequency is less than or equal to an error frequency associated with a tolerable packet error.

19. The apparatus of claim 18, wherein the adjusted sampling frequency is calculated from a selected clock frequency and the number of virtual accumulators to sequentially implement.