Symmetric differential slicer

• US 7,567,628 B2
• Filed: 02/11/2005
• Issued: 07/28/2009
• Est. Priority Date: 12/13/2004
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Darabi, Hooman
• Primary Examiner(s): Liu; Shuwang
• Assistant Examiner(s): PATEL, DHAVAL V
• Application Number:
  US11/055,935
• Publication Number:
  US 20060126759A1
• Time in Patent Office: 1,628 Days
• Field of Search: 327/65
• US Class Current: 375/318
• CPC Class Codes: H04L 25/0274 Arrangements for ensuring balanced coupling
• CPC Class Codes: H04L 25/0296 Arrangements to ensure DC-balance

Abstract

A self-biasing slicer includes a self-biased differential transistor pair. As a result of the self-biasing, the slicer may receive input signals without the use of AC coupling. That is, a differential input signal may be fed directly to the inputs of the differential transistor pair. The differential pair circuit may incorporate a self-biased load and a self-biased current source. The slicer also may include a matched output stage with inverters that provide a rail-to-rail output. Here, the inverters may incorporate components that are matched with components of the differential pair.

Claims

1. A symmetric differential slicer comprising:

a differential transistor pair configured to receive a differential input signal;

a first transistor pair with coupled gate leads configured to provide current for each transistor of the differential transistor pair;

a second transistor pair with coupled gate leads, the second transistor pair coupled to the differential transistor pair to provide an initial differential output signal;

a third transistor pair with coupled gate leads configured to receive a first leg of the initial differential output signal to provide a first leg of an inverted differential output signal; and

a fourth transistor pair with coupled gate leads configured to receive a second leg of the initial differential output signal to provide a second leg of the inverted differential output signal.

2. The symmetric differential slicer of claim 1 wherein the second transistor pair provides a common mode signal at its coupled gate leads.

3. The symmetric differential slicer of claim 2 wherein the common mode signal is coupled to the coupled gate leads of the first transistor pair.

4. The symmetric differential slicer of claim 1 wherein drain leads of the first transistor pair are coupled to source leads of the differential transistor pair.

5. The symmetric differential slicer of claim 4 wherein the drain leads of the first transistor pair are coupled together.

6. The symmetric differential slicer of claim 1 wherein the second transistor pair comprises a pair of resistors respectively coupled between the coupled gate leads and each source lead of the second transistor pair.

7. The symmetric differential slicer of claim 6 wherein the source leads of the second transistor pair are coupled to drain leads of the differential transistor pair.

8. The symmetric differential slicer of claim 1 wherein:

a drain lead of a first transistor of the third transistor pair is coupled to a source lead of a second transistor of the third transistor pair; and

a drain lead of a first transistor of the fourth transistor pair is coupled to a source lead of a second transistor of the fourth transistor pair.

9. The symmetric differential slicer of claim 1 wherein the third transistor pair and the fourth transistor pair each comprise:

at least one transistor that is matched to at least one transistor in the first transistor pair; and

at least one transistor that is matched to at least one transistor in the second transistor pair.

10. The symmetric differential slicer of claim 1 wherein the differential output signal comprises a rail-to-rail signal.