Method to validate system configuration in a data storage and retrieval system

• US 7,567,886 B2
• Filed: 02/08/2005
• Issued: 07/28/2009
• Est. Priority Date: 04/18/2001
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Lyman, Joel Kenneth, Beeston, Ralph Thomas
• Primary Examiner(s): Wachsman; Hal D
• Application Number:
  US11/054,142
• Publication Number:
  US 20050149644A1
• Time in Patent Office: 1,631 Days
• Field of Search: 702182-185, 702/57, 702117-123, 702/186
• US Class Current: 702/182
• CPC Class Codes: G06F 15/177 Initialisation or configuration control processor initialisation G06F9/4405

Abstract

A data storage and retrieval system is disclosed which includes encoded information regarding known valid system configurations, nominal performance specifications for various I/O devices, and nominal performance specifications for various interconnecting communication buses. A method is disclosed to validate the apparent configuration of the data storage and retrieval system. A method is disclosed to evaluate the performance of each I/O device and interconnecting bus disposed within the data storage and retrieval system.

Claims

1. A method to evaluate the performance of input/output devices and interconnecting buses disposed in a data storage and retrieval system, wherein said data storage and retrieval system comprises a host computer comprising a first host bus adapter and a second host bus adapter, first information comprising one or more valid system configurations, and second information comprising an apparent system configuration, said method comprising the steps of:

supplying a library external to said host computer, wherein said library comprises a plurality of input/output devices, a plurality of data storage media disposed in a plurality of data storage cartridges which are stored in a plurality of storage slots, and one or more accessors to retrieve, transport, and insert, said plurality of data storage cartridges in said plurality of input/output devices,

supplying a first bus connecting said first host bus adapter to each of said plurality of input/output devices;

supplying a second bus connecting said second host bus adapter to each of said plurality of input/output devices;

providing third information via said first bus to one of said plurality of input/output devices, wherein said third information comprises a series of connect commands interspersed with a series of disconnect commands, wherein said connect commands are selected from the group consisting of read buffer commands and write buffer commands;

receiving fourth information via said first bus from said one of said plurality of input/output devices, wherein said fourth information comprises device status information, transmitted data, and bus access requests;

evaluating-the performance of said first bus;

comparing the performance of said first bus with nominal performance specifications for said first bus;

when determining that the performance of said first bus is not acceptable,

displaying an error message on said host computer;

when determining that the performance of said first bus is acceptable, placing said data storage and retrieval system in a ready state.

2. The method of claim 1, further comprising the steps of:

comparing the performance of said one of said plurality of input/output devices with nominal performance specifications for said plurality of input/output devices;

when determining that the performance of said one of said plurality of input/output devices is not acceptable,

displaying an error message on said host computer;

when determining that the performance of said one of said plurality of input/output devices is acceptable, placing said data storage and retrieval system in a ready state.

3. The method of claim 1, wherein said providing third information step further comprises providing said third information at a first maximum data transfer rate.

4. The method of claim 3, further comprising the steps of:

providing said third information via said first bus to each of said plurality of input/output devices; and

receiving said fourth information via said first bus from each of said plurality of input/output devices.

5. The method of claim 4, wherein said data retrieval system further comprises a second bus having a second maximum data transfer rate, said method further comprising the steps of:

providing fifth information via said second bus to said one of said plurality of input/output devices;

receiving sixth information via said second bus from said one of said plurality of input/output devices;

analyzing said sixth information; and

evaluating the performance of said second bus.

6. The method of claim 5, wherein said fifth information is selected from the group consisting of connect commands, disconnect commands, and combinations thereof.

7. The method of claim 6, further comprising the steps of:

providing said fifth information via said second bus to each of said plurality of input/output devices; and

receiving said sixth information via said second bus from each of said plurality of input/output devices.

8. A data storage and retrieval system a computer readable medium having computer readable program code disposed therein for evaluating the performance of input/output devices and interconnecting buses disposed within a data storage and retrieval system, wherein said data storage and retrieval system comprises a host computer comprising a first host bus adapter and a second host bus adapter, and a library external to said host computer comprising a plurality of input/output devices, a plurality of data storage media disposed in a plurality of data storage cartridges which are stored in a plurality of storage slots, and one or more accessors to retrieve, transport, and insert, said plurality of data storage cartridges in said plurality of input/output devices, said data storage and retrieval system further comprising a first bus connecting said first host bus adapter to each of said plurality of input/output devices, a second bus connecting said second host bus adapter to each of said plurality of input/output devices, first information comprising one or more valid system configurations, and second information comprising an apparent system configuration, the computer readable program code comprising a series of computer readable program steps to effect:

providing to one of said plurality of input/output devices third information via said first bus, wherein said third information comprises a series of connect commands interspersed with a series of disconnect commands, wherein said connect commands are selected from the group consisting of read buffer commands and write buffer commands;

receiving from said one of said plurality of input/output devices fourth information via said first bus;

analyzing said fourth information, wherein said fourth information comprises device status information, transmitted data, and bus access requests;

evaluating the performance of said first bus;

comparing the performance of said first bus with nominal performance specifications for said first bus;

when determining that the performance of said first bus is not acceptable, displaying an error message on said host computer;

when determining that the performance of said first bus is acceptable, placing said data storage and retrieval system in a ready state.

9. The data storage and retrieval system of claim 8,

said computer readable program code further comprising a series of computer readable program steps to effect:

comparing the performance of said one of said plurality of input/output devices with nominal performance specifications for said plurality of input/output devices;

when determining that the performance of said one of said plurality of input/output devices is not acceptable,

displaying an error message;

when determining that the performance of said one of said plurality of input/output devices is acceptable, placing said data storage and retrieval system in a ready state.

10. The data storage and retrieval system of claim 9, wherein said providing step further comprises providing said third information at said first maximum data transfer rate.

11. The data storage and retrieval system of claim 9, wherein said computer readable program code further comprises a series of computer readable program steps to effect providing said third information at said first maximum data transfer rate.

12. The data storage and retrieval system of claim 11, wherein said computer readable program code further comprises a series of computer readable program steps to effect:

providing said third information via said first bus to each of said plurality of input/output devices; and

receiving said fourth information via said first bus from each of said plurality of input/output devices.

13. The data storage and retrieval system of claim 12, further comprising a second bus having a second maximum data transfer rate, wherein said computer readable program code further comprises a series of computer readable program steps to effect:

providing fifth information via said second bus to said plurality of input/output devices;

receiving sixth information via said second bus from said plurality of input/output devices;

analyzing said sixth information; and

evaluating the performance of said second bus.

14. The data storage and retrieval system of claim 13, wherein said fifth information is selected from the group consisting of connect commands, disconnect commands, and combinations thereof.

15. The data storage and retrieval system of claim 14, wherein said computer readable program code further comprises a series of computer readable program steps to effect:

providing said fifth information via said second bus to each of said plurality of input/output devices; and

receiving said sixth information via said second bus from each of said plurality of input/output devices.

16. A computer program product encoded to an information storage medium and having computer readable program code embodied therein, said computer program product being usable with a programmable computer processor for evaluating the performance of input/output devices and interconnecting buses disposed within a data storage and retrieval system, wherein said data storage and retrieval system comprises a host computer comprising a first host bus adapter and a second host bus adapter, and a library external to said host computer comprising a plurality of input/output devices, a plurality of data storage media disposed in a plurality of data storage cartridges which are stored in a plurality of storage slots, and one or more accessors to retrieve, transport, and insert, said plurality of data storage cartridges in said plurality of input/output devices, said data storage and retrieval system further comprising a first bus to each of said plurality of input/output devices, a second bus connecting said second host bus adapter to each of said plurality of input/output devices, first information comprising one or more valid system configurations, and second information comprising an apparent system configuration, comprising:

computer readable program code which causes said programmable computer processor to provide third information via said first bus to one of said plurality of input/output devices, wherein said third information comprises a series of connect commands interspersed with a series of disconnect commands, wherein said connect commands are selected from the group consisting of read buffer commands and write buffer commands;

computer readable program code which causes said programmable computer processor to receive fourth information via said first bus from said one of said plurality of input/output devices, wherein said fourth information comprises device status information, transmitted data, and bus access requests;

computer readable program code which causes said programmable computer processor to compare the performance of said first bus with nominal performance specifications for said first bus;

computer readable program code which causes said programmable computer processor to determine that the performance of said first bus is not acceptable and to display an error message on said host computer;

computer readable program code which causes said programmable computer processor to determine that the performance of said first bus is acceptable and to place said data storage and retrieval system in a ready state.

17. The computer program product of claim 16, further comprising:

computer readable program code which causes said programmable computer processor to compare the performance of said one of said plurality of input/output devices with nominal performance specifications for said plurality of input/output devices;

computer readable program code which causes said programmable computer processor to determine that the performance of said plurality of input/output devices is not acceptable and to display an error message on said host computer;

computer readable program code which causes said programmable computer processor to determine that the performance of said plurality of input/output devices is acceptable and to place said data storage and retrieval system in a ready state.

18. The computer program product of claim 17, further comprising:

computer readable program code which causes said programmable computer processor to provide said third information via said first bus to each of said plurality of input/output devices; and

computer readable program code which causes said programmable computer processor to receive said fourth information via said first bus from each of said plurality of input/output devices.

19. The computer program product of claim 18, wherein said data storage and retrieval system further comprises a second bus having a second maximum data transfer rate, further comprising:

computer readable program code which causes said programmable computer processor to provide fifth information via said second bus to said plurality of input/output devices;

computer readable program code which causes said programmable computer processor to receive sixth information via said second bus from said plurality of input/output devices;

computer readable program code which causes said programmable computer processor to analyze said sixth information; and

computer readable program code which causes said programmable computer processor to evaluate the performance of said second bus;

wherein said fifth information is selected from the group consisting of connect commands, disconnect commands, and combinations thereof.

20. The computer program product of claim 19, further comprising:

computer readable program code which causes said programmable computer processor to provide said fifth information via said second bus to each of said plurality of input/output devices; and

computer readable program code which causes said programmable computer processor to receive said sixth information via said second bus from each of said plurality of input/output devices.