Power delivery and power management of many-core processors

• US 7,568,115 B2
• Filed: 09/28/2005
• Issued: 07/28/2009
• Est. Priority Date: 09/28/2005
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Garver, Shu-ling, Karnik, Tanay, Borkar, Shekhar
• Primary Examiner(s): BUTLER, DENNIS
• Application Number:
  US11/238,489
• Publication Number:
  US 20070070673A1
• Time in Patent Office: 1,399 Days
• Field of Search: 713300-320, 713/323, 713/324
• US Class Current: 713/300
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/16 the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

According to embodiments of the disclosed subject matter in this application, a power management system with multiple voltage regulator (“VRs”) may be used to supply power to cores in a many-core processor. Each VR may supply power to a core or a part of a core. Different VRs may provide multiple voltages to a core/part in the many-core processor. The value of the output voltage of a VR may be modulated under the direction of the core/part to which the voltage regulator supplies power. In one embodiment, the multiple VRs may be integrated with cores in a single die. In another embodiment, the power management system with multiple VRs may be on a die (“the VR die”) separate from the die of the many-core processor. The VR die may be included in the same package as the many-core processor die.

Claims

1. An apparatus for managing power for an integrated circuit, comprising:

a package substrate;

a first die of a voltage regulator module, said first die mounted on said package substrate, said voltage regulator module including a plurality of voltage regulators; and

a second die of said integrated circuit, said package substrate, said first die, and said second die packed in the same package, said integrated circuit including a plurality of electronic units, wherein each voltage regulator in said first die is electronically coupled to said second die to supply power for and to provide a body bias signal to one or more electronic units in said second die based on specific conditions of said one or more electronic units to optimize power consumption.

2. The apparatus of claim 1, wherein said second die comprises input/output (I/O) interconnects for said plurality of electronic units, said I/O interconnects including interconnects for voltage identification (“

VID”

) signals.

3. The apparatus of claim 2, wherein said VID signals comprise a request from an electronic unit in said second die for a voltage supply with a specific value to a voltage regulator in said first die, said specific value being determined based on specific condition of said electronic unit, wherein upon receiving said request, said voltage regulator supplies said electronic unit with a voltage of said specific value.

4. The apparatus of claim 2, wherein said package substrate is between said first die and said second die.

5. The apparatus of claim 1, wherein each voltage regulator in said first die is aligned with one or more electronic units in said second die, to which the voltage regulator supplies power.

6. The apparatus of claim 1, wherein said integrate circuit comprises a many-core processor, said many-core processor including a plurality of cores, each of said plurality of electronic units including one of said plurality of cores.

7. The apparatus of claim 1, wherein said specific conditions of said one or more electronic units comprise one of software application running on, temperature of, transient current consumption by, reliability of, activeness of, working frequency required by, said one of more electronic units.

8. An apparatus for managing power for an integrated circuit, comprising:

a package substrate; and

a die mounted on said package substrate, said die including said integrated circuit and a plurality of voltage regulators, said integrated circuit including a plurality of electronic units, wherein each of said plurality of voltage regulators supplies power for and to provide a body bias signal to one or more of said plurality of electronic units based on specific conditions of said one or more electronic units to optimize power consumption.

9. The apparatus of claim 8, wherein said die comprises input/output (I/O) interconnects for said plurality of electronic units and interconnects for voltage identification (“

VID”

) signals.

10. The apparatus of claim 9, wherein said VID signals comprise a request from an electronic unit for a voltage supply with a specific value to a voltage regulator, wherein upon receiving said request, said specific value being determined based on specific condition of said electronic unit, said voltage regulator supplies said electronic unit with a voltage of said specific value.

11. The apparatus of claim 8, wherein said integrate circuit comprises a many-core processor, said many-core processor including a plurality of cores, each of said plurality of electronic units including one of said plurality of cores.

12. The apparatus of claim 8, wherein said specific conditions of said one or more electronic units comprise one of software application running on, temperature of, transient current consumption by, reliability of, activeness of, working frequency required by, said one of more electronic units.

13. A computing system, comprising:

a many-core processor, said many-core processor including a plurality of cores;

a non-volatile memory to store data for said many-core processor; and

a plurality of voltage regulators to provide power to said plurality of cores;

wherein each of said plurality of voltage regulators is located in proximity to one or more of said plurality of cores to which the voltage regulator supplies power (“

power-receiving object”

), and is capable of providing a voltage supply with a specific value requested by the power-receiving object to the power-receiving object and of providing a body bias signal to the power-receiving object, said specific value being determined based on specific condition of the power-receiving object to optimize power consumption of the many-core processor.

14. The system of claim 13, further comprising interconnects for voltage identification (“

VID”

) signals, said VID signals including a request from one of said plurality of cores for a voltage supply with a specific value to one of said plurality of voltage regulators, wherein upon receiving said request, said voltage regulator supplies said core with a voltage of said specific value, said specific value being determined based on specific condition of said core.

15. The system of claim 13, wherein said plurality of voltage regulators reside on a first die and said plurality of cores reside on a second die, said first die and said second die packed with a package substrate in the same package, wherein each voltage regulator in said first die is electronically coupled to said second die to supply power for one or more cores in said second die.

16. The system of claim 15, wherein said package substrate is between said first die and said second die.

17. The system of claim 15, wherein said first die is between said second die and said package substrate.

18. The system of claim 13, wherein said plurality of cores and said plurality of voltage regulators reside on a die, said die packaged with a package substrate.

19. The system of claim 13, further comprising a cooling system thermally coupled to at least one of said many-core processor and said plurality of voltage regulators to dissipate heat generated by at least one of said many-core processor and said plurality of voltage regulators.

20. The system of claim 13, wherein specific condition of the power-receiving object comprises one of software application running on, temperature of, transient current consumption by, reliability of, activeness of, working frequency required by, the power-receiving object.