Use of alternative value in cell detection

• US 7,568,135 B2
• Filed: 03/30/2007
• Issued: 07/28/2009
• Est. Priority Date: 05/15/2006
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Cornwell, Michael J., Dudte, Christopher P.
• Primary Examiner(s): Trimmings; John P
• Application Number:
  US11/694,728
• Publication Number:
  US 20070277060A1
• Time in Patent Office: 851 Days
• Field of Search: None
• US Class Current: 714/721
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

A system and method, including computer software, allows reading data from a flash memory cell. Voltages from a group of memory cells are detected. The group of memory cells have associated metadata for error detection, and each memory cell stores a voltage representing a data value selected from multiple possible data values. Each possible data value corresponds to one range of multiple non-overlapping ranges of analog voltages. Memory cells having uncertain data values are identified based on the detected voltages. Alternative data values for the memory cells having the uncertain data values are determined, and a combination of alternative data values is selected. An error detection test is performed using the metadata associated with the multiple memory cells and the selected combination of alternative data values.

Claims

1. A method for reading data from a flash memory cell, the method comprising:

detecting voltages from a group of memory cells, the group of memory cells having associated metadata for error detection, each memory cell storing a voltage representing a data value selected from a plurality of possible data values, each possible data value corresponding to one range of a plurality of non-overlapping ranges of analog voltages;

identifying memory cells having uncertain data values based on the detected voltages;

determining alternative data values for the memory cells having the uncertain data values;

selecting a combination of alternative data values; and

performing an error detection test using the metadata associated with the plurality of memory cells and the selected combination of alternative data values.

2. The method of claim 1, wherein the memory cells having uncertain data values are identified by identifying memory cells having detected voltages that fail to fall within one of the ranges of the plurality of non-overlapping ranges of analog voltages.

3. The method of claim 1, wherein the memory cells having uncertain data values are identified by identifying memory cells having detected voltages that fall near a boundary of one of the ranges of the plurality of non-overlapping ranges of analog voltages.

4. The method of claim 1, wherein the memory cells having uncertain data values are identified based at least in part on an error correction code.

5. The method of claim 1, wherein the alternative data values comprise nearest adjacent data values, each nearest adjacent data value for each memory cell determined by identifying the possible data value corresponding with the closest range of analog voltages to the detected voltage.

6. The method of claim 1, wherein the alternative data values comprise next nearest adjacent data values, each next nearest adjacent data value for each memory cell determined by finding the possible data corresponding with the second closest range of analog voltages to the detected voltage.

7. The method of claim 1, further comprising:

converting the detected voltage for each memory cell into a digital representation of the detected voltage, wherein identifying memory cells with uncertain data values and determining the alternative data values comprise comparing the digital representation of the detected voltage with stored digital data representing the plurality of non-overlapping ranges of analog voltages and the corresponding possible data values.

8. The method of claim 1, further comprising:

adjusting the detected voltage for each memory cell based upon heuristics.

9. The method of claim 8, wherein the heuristics are selected from the group consisting of reference cell voltage, read usage of the memory cell, write usage of the memory cell, temperature, product age, supply voltage, detected error levels, and combinations thereof.

10. The method of claim 1, wherein the group of memory cells comprise NAND flash memory cells.

11. The method of claim 1, wherein the group of memory cells comprises a page of memory cells.

12. The method of claim 1, wherein the group of memory cells comprises NOR flash memory cells.

13. The method of claim 1, wherein the error detection test uses error correction codes to determine the presence of an error.

14. The method of claim 1, further comprising:

correcting detected errors by using error correction code sequences, wherein correcting the detected errors comprises first using a hardware based error correction code, and then using a software based extended error correction code upon the failure of the hardware based error correction code to correct the detected errors.

15. A system for reading flash memory cells, the system comprising:

a group of memory cells, each memory cell adapted to receive a charge during a writer operation to a voltage level representing a data value selected from a group of possible data values, each possible data value corresponding to one range of a plurality of non-overlapping ranges of voltages;

a set of memory cells associated with the group of memory cells, the set of memory cells adapted to store metadata for correcting errors associated with the group of memory cells;

a voltage detector adapted to receive voltage signals from each memory cells; and

a processor adapted to;

determine alternative data values for each cell having an uncertain data value;

select a combination of alternative data values; and

use the metadata and the combination of alternative data values to perform error correction.

16. The system of claim 15, wherein the processor is adapted to repetitively select a combination of alternative data values and use the metadata and the combinations of alternative data values to perform error correction until either identifying an error-free combination or exhausting all possible combinations.

17. The system of claim 15, wherein the processor is adapted to identify memory cells having uncertain data values by comparing the voltage signals to the plurality of non-overlapping ranges of voltages.

18. The system of claim 15, wherein the alternative data values comprise at least one of nearest adjacent data values or next nearest adjacent data values.

19. The system of claim 15, further comprising:

an analog-to-digital converter to convert the voltage signal from each memory cell into a digital representation of the voltage signal.

20. The system of claim 15, wherein the group of memory cells comprise a page of NAND flash memory cells.

21. The system of claim 15, wherein the group of memory cells comprises NOR flash memory cells.

22. The system of claim 15, wherein the metadata comprises error correction codes.

23. The system of claim 15, further comprising:

a buffer to store selected combinations of alternative data values along with data values for memory cells not having uncertain data values, wherein the processor is adapted to use the data values stored in the buffer in determining whether the selected combination contains an error.

24. An article of manufacture comprising machine-readable instructions that, when executed, cause operations to be performed, the operations comprising:

receiving a voltage signal from a group of memory cells during a read operation, the voltage corresponding to a data value selected from a group of possible data values, each possible data value corresponding to one range of a plurality of non-overlapping ranges of voltages;

determining alternative data values for each cell having an uncertain data value;

selecting a combination of alternative data values; and

performing an error detection test using the metadata to determine if the combination of alternative data values contains an error.

25. The article of claim 24, the operations further comprising:

repeating the operations of selecting combinations of alternative data values and performing the error detection test until an error-free combination is found or until all possible combinations are exhausted.

26. The article of claim 24, the operations further comprising:

copying the selected combinations of alternative data values into a buffer prior to performing the error detection test.

27. The article of claim 24, the operations further comprising:

converting the voltage signal into a digital representation of the voltage signal.

28. A system for reading flash memory cells, the system comprising:

a group of memory cells, each memory cell adapted to store a charge representing a data value selected from a group of possible data values, each possible data value corresponding to one of a group of non-overlapping ranges of voltages;

a converter for converting the voltage for each memory cell into a digital representation; and

means for determining alternative data values for each cell having an uncertain data value;

means for selecting a combination of alternative data values; and

means for performing error correction on data values stored in the group of memory cells using the selected combination of alternative data values.

29. The system of claim 28, wherein the group of memory cells comprise NAND flash memory cells.

30. The system of claim 28, wherein the group of memory cells comprise multi-level flash memory cells each comprising more than 4 bits.

31. The system of claim 28, further comprising:

means for correcting data values in the selected combination of alternative data values.

32. The system of claim 28, wherein the means for performing error correction on data values stored in the group of memory cells using the selected combination of alternative data values further uses data values from memory cells not identified as having uncertain data values.