Gate critical dimension variation by use of ghost features

• US 7,569,309 B2
• Filed: 11/09/2005
• Issued: 08/04/2009
• Est. Priority Date: 11/09/2005
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Rathshack, Benjamen Michael, Blatchford, James Walter
• Primary Examiner(s): ROSASCO, STEPHEN D
• Application Number:
  US11/269,633
• Publication Number:
  US 20070105387A1
• Time in Patent Office: 1,364 Days
• Field of Search: 430/5, 430/394, 716/19, 716/21
• US Class Current: 430/5
• CPC Class Codes: H01L 21/0334 characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
• CPC Class Codes: H01L 21/28123 Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects

Abstract

According to various embodiments, the present teachings include various methods for forming a semiconductor device, computer readable medium for forming a semiconductor device, mask sets for forming a semiconductor device, and a semiconductor device made according to various methods. For example, a method can comprise forming a first feature and a second feature on a substrate by exposing a first mask to a first beam, wherein the second feature is disposed adjacent to the first feature, exposing a second mask to a second beam, and removing the second feature from the substrate.

Claims

1. A computer readable medium containing program code that configures a processor to perform a method of making masks for forming an array of features on a semiconductor device, comprising:

program code for forming a first mask feature on a first mask to provide a first feature in the array of features on the semiconductor device and a second mask feature on the first mask adjacent to, and spaced from, the first mask feature to provide a second feature adjacent to, and spaced from, the first feature in the array of features on the semiconductor device; and

program code for forming a second mask to be used in conjunction with the first mask, the second mask comprising,

a first region that blocks radiation and that corresponds to the first mask feature and the first feature in the array of features on the semiconductor device, and

a second region that permits radiation to impinge on an entirety of the second feature in the array of features on the semiconductor device.

2. The computer readable medium containing program code that configures a processor to perform a method of making masks according to claim 1, wherein the second mask feature forms a ghost feature on a substrate.

3. The computer readable medium containing program code that configures a processor to perform a method of making masks according to claim 2 further comprising:

program code for forming a plurality of first mask features, where each of the first mask features are spaced from each other at a first pitch, and wherein the ghost mask feature is spaced from the one of the first mask features by a second pitch.

4. The computer readable medium containing program code that configures a processor to perform a method of making masks according to claim 3, wherein the first pitch is the same as the second pitch.

5. The computer readable medium containing program code that configures a processor to perform a method of making masks according to claim 1, wherein the program code for forming the first mask forms an alternating phase shift mask.

6. The computer readable medium containing program code that configures a processor to perform a method of making masks according to claim 1, wherein the first mask feature on the first mask patterns a first gate on the substrate, the second mask feature on the first mask patterns a second gate on the substrate, and the second region of the second mask is provided to allow complete removal of the second gate from the substrate.