Mobility enhanced CMOS devices

• US 7,569,848 B2
• Filed: 02/28/2006
• Issued: 08/04/2009
• Est. Priority Date: 03/03/2004
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Doris, Bruce B., Belyansky, Michael P., Gluschenkov, Oleg G.
• Primary Examiner(s): Huynh; Andy
• Application Number:
  US11/362,773
• Publication Number:
  US 20060148147A1
• Time in Patent Office: 1,253 Days
• Field of Search: 257/19, 257/57, 257/192, 257/213, 257/E21.546, 257/E29.104, 257/E29.193, 257/E31.035, 257/E33.009
• US Class Current: 257/19
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

Compressive or tensile materials are selectively introduced beneath and in alignment with spacer areas and adjacent to channel areas of a semiconductor substrate to enhance or degrade electron and hole mobility in CMOS circuits. A process entails steps of creating dummy spacers, forming a dielectric mandrel (i.e., mask), removing the dummy spacers, etching recesses into the underlying semiconductor substrate, introducing a compressive or tensile material into a portion of each recess, and filling the remainder of each recess with substrate material.

Claims

1. A semiconductor structure, comprising:

a substrate;

a field effect transistor gate on the substrate, the gate having a first side and a second side;

a first spacer against a first side of the gate;

a second spacer against a second side of the gate;

a first recess in the substrate, the first recess being approximately directly below the first spacer and having a first side approximately in alignment with the first side of the gate;

a second recess in the substrate, the second recess being approximately directly below the second spacer and having a second side approximately in alignment with the second side of the gate;

a material imposing stress filling a first portion of the first recess and a first portion of the second recess;

a semiconductor material filling a second portion of the first recess and a second portion of the second recess.

2. A semiconductor structure according to claim 1, wherein the stress imposing material is a material that introduces one of a compressive stress and a tensile stress.

3. A semiconductor structure according to claim 1, wherein the stress imposing material is a material comprised of at least one of polysilicon, SiO₂, Si_1-xGe_x, Si_xON_y, or Si_xON_y.

4. A semiconductor structure according to claim 1, wherein:

the gate is an n-channel field effect transistor gate or a p-channel field effect transistor gate; and

the stress imposing material is a material that introduces a tensile stress in a direction parallel to a direction of current flow if the gate is an n-channel field effect transistor gate, or a material that introduces a compressive stress in a direction parallel to a direction of current flow if the gate is a p-channel field effect transistor gate.

5. A semiconductor structure according to claim 1, wherein:

the stress imposing material is a material that introduces a stress that enhances or degrades electron or hole mobility in the semiconductor structure.