Dual crystal orientation circuit devices on the same substrate

• US 7,569,857 B2
• Filed: 09/29/2006
• Issued: 08/04/2009
• Est. Priority Date: 09/29/2006
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Kavalieros, Jack T, Datta, Suman, Doyle, Brian S, Tolchinsky, Peter
• Primary Examiner(s): Tran; Minh-Loan T
• Assistant Examiner(s): KUO, WENSING W
• Application Number:
  US11/529,974
• Publication Number:
  US 20080079003A1
• Time in Patent Office: 1,040 Days
• Field of Search: 257/64,69,70,627,369,401,E29.004
• US Class Current: 257/69
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

Embodiments of the invention provide a substrate with a device layer having different crystal orientations in different portions or areas. One layer of material having one crystal orientation may be bonded to a substrate having another crystal orientation. Then, a portion of the layer may be amorphized and annealed to be re-crystallized to the crystal orientation of the substrate. N- and P-type devices, such as tri-gate devices, may both be formed on the substrate, with each type of device having the proper crystal orientation along the top and side surfaces of the claimed region for optimum performance. For instance, a substrate may have a portion with a <100> crystal orientation along a top and sidewalls of an NMOS tri-gate transistor and another portion having a <110> crystal orientation along parallel top and sidewall surfaces of a PMOS tri-gate transistor.

Claims

1. A device comprising:

a first channel region on a substrate and having a first plurality of channel surfaces to be biased by a plurality of gate surfaces of a gate structure, wherein the channel surfaces have a first same crystal orientation;

a second channel region on the substrate, the second channel region having a second plurality of channel surfaces to be biased by a plurality of gate surfaces of the gate structure, wherein the channel surfaces have a second same crystal orientation; and

wherein the first channel extends above and touches a semiconductor surface of the substrate having the second same crystal orientation, the second channel extends above and touches a semiconductor surface of a layer on the substrate having the second same crystal orientation, and the first plurality of channel surfaces are parallel with the second plurality of channel surfaces.

2. The device of claim 1 wherein the plurality of channel surfaces comprise a top surface, a left side surface, and a right side surface comprising a same crystal orientation of a <

100>

crystal orientation or a <

110>

crystal orientation.

3. The device of claim 2 wherein the substrate is a bulk substrate, the first same crystal orientation is a <

110>

crystal orientation, and the second same crystal orientation is a <

100>

crystal orientation.

4. The device of claim 1, wherein the semiconductor surface of the substrate having the second same crystal orientation and the semiconductor surface of a layer on the substrate having the second same crystal orientation are the same semiconductor material.