Integrated circuit using complementary junction field effect transistor and MOS transistor in silicon and silicon alloys

• US 7,569,873 B2
• Filed: 10/28/2005
• Issued: 08/04/2009
• Est. Priority Date: 10/28/2005
• Status: Expired due to Fees

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: SuVolta, Inc.
• Inventors: Kapoor, Ashok K.
• Primary Examiner(s): Nguyen, Dao H
• Application Number:
  US11/261,873
• Publication Number:
  US 20070096144A1
• Time in Patent Office: 1,376 Days
• Field of Search: 257/134, 257/256, 257/272, 257/274, 438/186, 438/194
• US Class Current: 257/256
• CPC Class Codes: H01L 21/2257 the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
• CPC Class Codes: H01L 27/0611 integrated circuits having a two-dimensional layout of components without a common active region
• CPC Class Codes: H01L 27/098 the components being PN junction gate field-effect transistors
• CPC Class Codes: H01L 29/41783 Raised source or drain electrodes self aligned with the gate
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66492 with a pocket or a lightly doped drain selectively formed at the side of the gate
• CPC Class Codes: H01L 29/66901 with a PN homojunction gate
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/808 with a PN junction gate , e.g. PN homojunction gate H01L29/7725, H01L29/775, H01L29/778, H01L29/806 take precedence

Abstract

This invention describes a method of building complementary logic circuits using junction field effect transistors in silicon. This invention is ideally suited for deep submicron dimensions, preferably below 65 nm. The basis of this invention is a complementary Junction Field Effect Transistor which is operated in the enhancement mode. The speed-power performance of the JFETs becomes comparable with the CMOS devices at sub-70 nanometer dimensions. However, the maximum power supply voltage for the JFETs is still limited to below the built-in potential (a diode drop). To satisfy certain applications which require interface to an external circuit driven to higher voltage levels, this invention includes the structures and methods to build CMOS devices on the same substrate as the JFET devices.

Claims

1. A junction field effect transistor, comprising:

a semiconductor substrate;

a first impurity region of a first conductivity type which is formed in the substrate;

a second impurity region of the first conductivity type which is formed in the substrate and spaced apart from the first impurity region;

a channel region of the first conductivity type which is located between the first and second impurity regions, wherein the channel region has a maximum length of less than 100 nm;

a gate electrode region of a second conductivity type which is formed above the top surface of the semiconductor substrate; and

a gate region of the second conductivity type which is formed in the substrate;

wherein the channel region has sidewalls that are substantially aligned with sidewalls of the gate electrode region and with sidewalls of the gate region.

2. The junction field effect transistor of claim 1, wherein at least a portion of the gate electrode region comprises a polycrystalline alloy comprising at least silicon and carbon.

3. The junction field effect transistor of claim 2, wherein the gate electrode region further comprises at least one of:

germanium, gallium, aluminum, arsenide, and phosphide.

4. The junction field effect transistor of claim 1, wherein the gate electrode region comprises polycrystalline silicon.

5. The junction field effect transistor of claim 1, wherein the gate electrode region comprises a plurality of polycrystalline alloy layers.

6. The junction field effect transistor of claim 1, wherein:

the first impurity region comprises a source region; and

the second impurity region comprises a drain region.

7. The junction field effect transistor of claim 6, further comprising:

a source electrode region of the first conductivity type which is formed above the top surface of the semiconductor substrate; and

a drain electrode region of the first conductivity type which is formed above the top surface of the semiconductor substrate.

8. The junction field effect transistor of claim 7, wherein:

the source electrode region comprises polycrystalline silicon; and

the drain electrode region comprises polycrystalline silicon.

9. The junction field effect transistor of claim 7, wherein at least a portion of the source region comprises impurities that were diffused from the source electrode region.

10. The junction field effect transistor of claim 7, wherein at least a portion of the drain region comprises impurities that were diffused from the drain electrode region.

11. The junction field effect transistor of claim 7, further comprising a source contact region formed on the source electrode region and in ohmic contact with the source region.

12. The junction field effect transistor of claim 7, further comprising a drain contact region formed on the drain electrode region and in ohmic contact with the drain region.

13. The junction field effect transistor of claim 7, wherein at least a portion of the source electrode region comprises a polycrystalline alloy comprising at least silicon and carbon.

14. The junction field effect transistor of claim 7, wherein at least a portion of the drain electrode region comprises a polycrystalline alloy comprising at least silicon and carbon.

15. The junction field effect transistor of claim 6, wherein:

the source region comprises a first source portion and a second source portion; and

the first source portion connects the second source portion and the channel region.

16. The junction field effect transistor of claim 15, wherein the first source portion has an impurity concentration that is doped independently of the second source portion.

17. The junction field effect transistor of claim 6, wherein:

the drain region comprises a first drain portion and a second drain portion; and

the first drain portion connects the second drain portion and the channel region.

18. The junction field effect transistor of claim 17, wherein the first drain portion has an impurity concentration that is doped independently of the second drain portion.

19. The junction field effect transistor of claim 1, wherein:

the gate electrode region comprises a first boundary and a second boundary; and

the gate region comprises a first boundary, a second boundary, and a third boundary, wherein the third boundary abuts the gate electrode region and the first boundary is substantially aligned with the first boundary of the gate electrode region.

20. The junction field effect transistor of claim 19, wherein the second boundary of the gate region is substantially aligned with the second boundary of the gate electrode region.

21. The junction field effect transistor of claim 1, wherein the gate region comprises impurities that were diffused from the gate electrode region.

22. The junction field effect transistor of claim 1, wherein:

the gate region comprises a first boundary and a second boundary;

the channel region comprises a first boundary, a second boundary, and a third boundary, wherein the third boundary abuts the gate region and at least a portion of the first boundary of the channel region is substantially aligned with the first boundary of the gate region.

23. The junction field effect transistor of claim 22, wherein at least a portion of the second boundary of the channel region is substantially aligned with the second boundary of the gate region.

24. The junction field effect transistor of claim 1, wherein the gate electrode region is substantially aligned with the gate region.

25. The junction field effect transistor of claim 1, further comprising:

a source electrode region; and

a drain electrode region;

wherein the source electrode region, the drain electrode region, and the gate electrode region have substantially coplanar surfaces.

26. The junction field effect transistor of claim 1, wherein:

the first conductivity type comprises n-type; and

the second conductivity type comprises p-type.

27. The junction field effect transistor of claim 1, wherein:

the first conductivity type comprises p-type; and

the second conductivity type comprises n-type.

28. The junction field effect transistor of claim 1, further comprising a well region formed in the semiconductor substrate;

wherein;

the first impurity region, the second impurity region, the gate region, and the channel region are formed in the well region;

the semiconductor substrate comprises the first conductivity type; and

the well region comprises the second conductivity type.

29. The junction field effect transistor of claim 28, wherein the well region comprises a floating well region.

30. The junction field effect transistor of claim 28, further comprising an insulating region formed in the semiconductor substrate and surrounding at least a portion of the well region.

31. The junction field effect transistor of claim 1, further comprising a gate contact region formed on the gate electrode region and in ohmic contact with the gate region.

32. The junction field effect transistor of claim 31, wherein the gate contact region comprises silicide.

33. The junction field effect transistor of claim 31, wherein the gate contact region is substantially aligned with the gate region.

34. The junction field effect transistor of claim 31, wherein the gate contact region is substantially aligned with the channel region.

35. The junction field effect transistor of claim 1, wherein at least one of the channel region and the gate region are formed of epitaxially deposited silicon-germanium-carbon alloy material.

36. The junction field effect transistor of claim 1, wherein the channel conducts a current at an operating voltage equal to or less than 0.5 volts.

37. The junction field effect transistor of claim 1, wherein the channel region is doped with a weaker impurity concentration than the first impurity region and the second impurity region.

38. The junction field effect transistor of claim 37, wherein the transistor comprises an enhancement-mode transistor.

39. The junction field effect transistor of claim 24, wherein the alignment of the gate region with the gate electrode region reduces the capacitance of the junction field effect transistor.

40. An electronic circuit comprising one or more devices wherein at least one device in the electronic circuit comprises a junction field effect transistor that comprises:

a semiconductor substrate;

a first impurity region of a first conductivity type which is formed in the substrate;

a second impurity region of the first conductivity type which is formed in the substrate and spaced apart from the first impurity region;

a channel region of the first conductivity type which is located between the first and second impurity regions, wherein the channel region has a maximum length of less than 100 nm;

a gate electrode region of a second conductivity type which is formed above the top surface of the semiconductor substrate; and

a gate region of the second conductivity type which is formed in the substrate;

wherein the channel region has sidewalls that are substantially aligned with sidewalls of the gate electrode region and with sidewalls of the gate region.

41. The electronic circuit of claim 40,wherein:

the junction field effect transistor comprises an n-channel JFET; and

at least one of the one or more devices comprises a p-channel JFET.

42. The electronic circuit of claim 41, wherein the n-channel JFET and the p-channel JFET operate as an inverter circuit.

43. The electronic circuit of claim 40, wherein at least a portion of the gate electrode region of the JFET comprises a polycrystalline alloy comprising at least silicon and carbon.

44. The electronic circuit of claim 40, wherein:

the first impurity region comprises a source region; and

the second impurity region comprises a drain region.

45. The electronic circuit of claim 44, wherein the junction field effect transistor further comprises:

a source electrode region of the first conductivity type which is formed above the top surface of the semiconductor substrate; and

a drain electrode region of the first conductivity type which is formed above the top surface of the semiconductor substrate.

46. The electronic circuit of claim 45, wherein at least a portion of the source region comprises impurities that were diffused from the source electrode region.

47. The electronic circuit of claim 45, wherein at least a portion of the drain region comprises impurities that were diffused from the drain electrode region.

48. The electronic circuit of claim 44, wherein:

the source region comprises a first source portion and a second source portion; and

the first source portion connects the second source portion and the channel region.

49. The electronic circuit of claim 44, wherein:

the drain region comprises a first drain portion and a second drain portion; and

the first drain portion connects the second drain portion and the channel region.

50. The electronic circuit of claim 40, wherein:

the gate electrode region comprises a first boundary and a second boundary; and

the gate region comprises a first boundary, a second boundary, and a third boundary, wherein the third boundary abuts the gate electrode region and the first boundary of the gate region is substantially aligned with the first boundary of the gate electrode region.

51. The electronic circuit of claim 50, wherein the second boundary of the gate region is substantially aligned with the second boundary of the gate electrode region.

52. The electronic circuit of claim 50, wherein the alignment of the gate region with the gate electrode region reduces the capacitance of the junction field effect transistor.

53. The electronic circuit of claim 40, wherein:

the gate region comprises a first boundary and a second boundary;

the channel region comprises a first boundary, a second boundary, and a third boundary, wherein the third boundary abuts the gate region and at least a portion of the first boundary of the channel region is substantially aligned with the first boundary of the gate region.

54. The electronic circuit of claim 40, wherein the gate region comprises impurities that were diffused from the gate electrode region.

55. The electronic circuit of claim 40, wherein the junction field effect transistor further comprises:

a source electrode region; and

a drain electrode region;

wherein the source electrode region, the drain electrode region, and the gate electrode region have substantially coplanar surfaces.

56. The electronic circuit of claim 40, wherein:

the first conductivity type comprises n-type; and

the second conductivity type comprises p-type.

57. The electronic circuit of claim 40, wherein:

the first conductivity type comprises p-type; and

the second conductivity type comprises n-type.

58. The electronic circuit of claim 40, wherein the junction field effect transistor further comprises a well region formed in the semiconductor substrate;

wherein;

the first impurity region, the second impurity region, the gate region, and the channel region are formed in the well region;

the semiconductor substrate comprises the first conductivity type; and

the well region comprises the second conductivity type.

59. The electronic circuit of claim 40, wherein the junction field effect transistor further comprises a gate contact region formed on the gate electrode region and in ohmic contact with the gate region.

60. The electronic circuit of claim 59, wherein the gate contact region comprises silicide.

61. The electronic circuit of claim 59, wherein the gate contact region is substantially aligned with the gate region.

62. The electronic circuit of claim 59, wherein the gate contact region is substantially aligned with the channel region.

63. The electronic circuit of claim 40, wherein the channel conducts a current at an operating voltage equal to or less than 0.5 volts.

64. The electronic circuit of claim 40, wherein the channel region is doped with a weaker impurity concentration than the first impurity region and the second impurity region.

65. The electronic circuit of claim 64, wherein the transistor comprises an enhancement-mode transistor.

66. The electronic circuit of claim 40, wherein:

the junction field effect transistor comprises a p-channel JFET; and

at least one of the one or more devices comprises a n-channel JFET.