Ternary content addressable memory (TCAM) cells with low signal line numbers
First Claim
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1. A ternary content addressable memory (TCAM) cell circuit formed in a TCAM memory cell array having cells arranged in rows and columns, comprising:
- a first storage circuit that stores a first data value and has a first data path coupled to a first storage node and a second data path coupled to a second storage node, the first data path and second data path are commonly coupled to a first word line;
a second storage circuit that stores a second data value and has a third data path coupled to a third storage node and a fourth data path coupled to a fourth storage node, the third data path and fourth data path are commonly coupled to a second word line;
a compare circuit that generates a match result at a match node based on the first data value, second data value, and a compare data value; and
no more than five conductive lines disposed in the column wise direction having a direct electrical connection to the TCAM cell for providing non-power supply signals, including a first bit line coupled to the first data path, a second bit line coupled to the third data path, and a third bit line coupled to the second and fourth data paths.
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Abstract
A ternary content addressable memory (TCAM) cell circuit formed in a TCAM memory cell array having cells arranged in rows and columns can include a first storage circuit with first and second data path, a second storage circuit with a third and fourth data path, and a compare circuit. No more than four conductive lines in a column wise direction have a direct electrical connection to the TCAM cell. Such conductive lines can include a first bit line coupled to the first data path and the third data path and a second bit line coupled to the second data path and the fourth data path.
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Citations
6 Claims
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1. A ternary content addressable memory (TCAM) cell circuit formed in a TCAM memory cell array having cells arranged in rows and columns, comprising:
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a first storage circuit that stores a first data value and has a first data path coupled to a first storage node and a second data path coupled to a second storage node, the first data path and second data path are commonly coupled to a first word line; a second storage circuit that stores a second data value and has a third data path coupled to a third storage node and a fourth data path coupled to a fourth storage node, the third data path and fourth data path are commonly coupled to a second word line; a compare circuit that generates a match result at a match node based on the first data value, second data value, and a compare data value; and no more than five conductive lines disposed in the column wise direction having a direct electrical connection to the TCAM cell for providing non-power supply signals, including a first bit line coupled to the first data path, a second bit line coupled to the third data path, and a third bit line coupled to the second and fourth data paths. - View Dependent Claims (2, 3, 4)
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5. A ternary content addressable memory (TCAM) cell circuit formed in a TCAM memory cell array having cells arranged in rows and columns, comprising:
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a first storage circuit that stores a first data value and has a first data path coupled to a first storage node and a second data path coupled to a second storage node; a second storage circuit that stores a second data value and has a third data path coupled to a third storage node and a fourth data path coupled to a fourth storage node; a compare circuit that generates a match result at a match node based on the first data value, second data value, and a compare data value; and no more than five conductive lines disposed in the column wise direction having a direct electrical connection to the TCAM cell for providing non-power supply signals, including a first bit line coupled to the first data path, a second bit line coupled to the third data path, and a third bit line coupled to the second and fourth data paths, wherein the no more than five conductive lines consists of three conductive lines, the first bit line being further coupled to the compare circuit, and the second bit line being further coupled to the compare circuit. - View Dependent Claims (6)
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Specification