Semiconductor memory device with adjustable selected work line potential under low voltage condition

• US 7,570,525 B2
• Filed: 07/25/2006
• Issued: 08/04/2009
• Est. Priority Date: 08/02/2005
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Tsukamoto, Yasumasa, Nii, Koji, Yabuuchi, Makoto, Ohbayashi, Shigeki
• Primary Examiner(s): NGUYEN, VAN THU T
• Application Number:
  US11/492,031
• Publication Number:
  US 20070030741A1
• Time in Patent Office: 1,106 Days
• Field of Search: 365/154.X, 365/189.01, 365/189.11 O, 365/230.03 X, 365/154, 365/230.03, 365/189.011, 365/189.11
• US Class Current: 365/189.11
• CPC Class Codes: G11C 11/4085 Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
• CPC Class Codes: G11C 11/417 for memory cells of the field-effect type
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

A level shift element adjusting a voltage level at the time of selection of a word line according to fluctuations in threshold voltage of a memory cell transistor is arranged for each word line. This level shift element lowers a driver power supply voltage, and transmits the level-shifted voltage onto a selected word line. The level shift element can be replaced with a pull-down element for pulling down the word line voltage according to the threshold voltage level of the memory cell transistor. In either case, the selected word line voltage level can be adjusted according to the fluctuations in threshold voltage of the memory cell transistor without using another power supply system. Thus, the power supply circuitry is not complicated, and it is possible to achieve a semiconductor memory device that can stably read and write data even with a low power supply voltage.

Claims

1. A semiconductor memory device comprising:

a plurality of static memory cells arranged in rows and columns, each memory cell including, in a data storage portion, a load transistor connected to a cell power supply node and a drive transistor connected in series to said load transistor;

a plurality of word lines, arranged corresponding to the respective memory cell rows, each connected to the memory cells in a corresponding row; and

a plurality of word line drivers arranged corresponding to the respective word lines, for driving corresponding word lines to a selected state according to a word line select signal, each word line driver including a level shift element for shifting a voltage level of a driver power supply node to a voltage level lower than a voltage of said driver power supply node, and for driving the corresponding word line to the voltage level level-shifted by said level shift element when the corresponding word line is selected, said level shift element being formed of a transistor element, having threshold voltage characteristics similar to those of said load transistor, of a same conductivity type as the load transistor.

2. The semiconductor memory device according to claim 1, wherein said transistor element comprises a plurality of unit transistors arranged in parallel with each other.

3. The semiconductor memory device according to claim 2, wherein

the load transistor of the memory cell comprises an insulated gate field effect transistor, and

each unit transistor has a ratio of a channel width to a channel length 0.5 to 5 times larger than a ratio of a channel width to a channel length of the load transistor.

4. A semiconductor memory device comprising:

a plurality of static memory cells arranged in rows and columns, each of the memory cells including, in a data storage portion, a load transistor connected to a cell power supply node and a drive transistor connected in series to said load transistor, the load transistor of the memory cell being formed of an insulated gate field effect transistor;

a plurality of word lines, arranged corresponding to the respective memory cell rows, each connected to the memory cells in a corresponding row; and

a plurality of word line drivers arranged corresponding to the respective word lines, for driving corresponding word lines to a selected state according to a word line select signal, each word line driver including a level shift element for shifting a voltage level of a driver power supply node to a voltage level lower than a voltage of said driver power supply node, and for driving the corresponding word line to the voltage level level-shifted by said level shift element when the corresponding word line is selected, said level shift element including a transistor element having a ratio of a channel width to a channel length being 0.5 to 5 times larger than a ratio of a channel width to a channel length of said load transistor.

5. A semiconductor memory device comprising:

a plurality of static memory cells arranged in rows and columns, each the memory cell including a load transistor having a first conduction node connected to a cell power supply node and having a gate electrode connected to an internal storage node;

a plurality of word lines, arranged corresponding to the respective memory cell rows, each connected to the memory cells in a corresponding row; and

a plurality of word line drivers arranged corresponding to the respective word lines, for driving corresponding word lines to a selected state according to a word line select signal, each word line driver including a level shift element for shifting a voltage level of a driver power supply node to a voltage level lower than a voltage of said driver power supply node, and for driving the corresponding word line to the voltage level level-shifted by said level shift element when the corresponding word line is selected, the level shift element comprising a transistor element having a gate electrode arranged extending in a same direction as the gate electrode of the load transistor.

6. A semiconductor memory device comprising:

a plurality of static memory cells arranged in rows and columns, each of the memory cells including, in a data storage portion, a load transistor connected to a cell power supply node and a drive transistor connected in series to said load transistor;

a plurality of word lines, arranged corresponding to the respective memory cell rows, each connected to the memory cells in a corresponding row;

a plurality of word line drivers arranged corresponding to the respective word lines, for driving corresponding word lines to a selected state according to a word line select signal; and

a plurality of pull-down elements, arranged corresponding to the respective word lines, each for lowering a voltage level of a corresponding word line when the corresponding word line is selected, each pull-down element being formed of a transistor element, having threshold voltage characteristics similar to those of said drive transistor, and of a same conductivity type as said drive transistor.

7. A semiconductor memory device comprising:

a plurality of static memory cells arranged in rows and columns, each of the memory cells including, in a data storage portion, a load transistor connected to a cell power supply node and a drive transistor connected in series to said load transistor, the drive transistor of each memory cell being formed of an insulated gate field effect transistor;

a plurality of word lines, arranged corresponding to the respective memory cell rows, each connected to the memory cells in a corresponding row;

a plurality of word line drivers arranged corresponding to the respective word lines, for driving corresponding word lines to a selected state according to a word line select signal; and

a plurality of pull-down elements, arranged corresponding to the respective word lines, each for lowering a voltage level of a corresponding word line when the corresponding word line is selected, each pull-down element including a transistor having a ratio of a channel width to a channel length being 0.5 to 5 times larger than a ratio of a channel width to a channel length of said drive transistor.

8. A semiconductor memory device comprising:

a plurality of static memory cells arranged in rows and columns;

a plurality of word lines, arranged corresponding to the respective memory cell rows, each connected to the memory cells in a corresponding row;

a plurality of word line drivers arranged corresponding to the respective word lines, for driving corresponding word lines to a selected state according to a word line select signal; and

a plurality of pull-down elements, arranged corresponding to the respective word lines, each for lowering a voltage level of a corresponding word line when the corresponding word line is selected, and each being formed of a transistor element rendered non-conductive in a data write operation according to a data write control signal.

9. A semiconductor memory device comprising:

a plurality of static memory cells arranged in rows and columns;

a plurality of word lines, arranged corresponding to the respective memory cell rows, each connected to the memory cells in a corresponding row;

a plurality of word line drivers arranged corresponding to the respective word lines, for driving corresponding word lines to a selected state according to a word line select signal; and

a plurality of pull-down elements, arranged corresponding to the respective word lines, each for lowering a voltage level of a corresponding word line when the corresponding word line is selected, said pull-down element being formed of a plurality of unit transistors arranged in parallel.

10. The semiconductor memory device according to claim 9, wherein

the drive transistor of the memory cell is formed of an insulated gate field effect transistor, and

each unit transistor has a ratio of a channel width to a channel length being 0.5 to 5 times larger than a ratio of a channel width to a channel length of said drive transistor.

11. A semiconductor memory device comprising:

a plurality of static memory cells arranged in rows and columns, each memory cell including a drive transistor connected in series to a load transistor connected to a cell power supply node, and having a gate electrode connected to a gate electrode of said load transistor;

a plurality of word lines, arranged corresponding to the respective memory cell rows, each connected to the memory cells in a corresponding row;

a plurality of word line drivers arranged corresponding to the respective word lines, for driving corresponding word lines to a selected state according to a word line select signal; and

a plurality of pull-down elements, arranged corresponding to the respective word lines, each for lowering a voltage level of a corresponding word line when the corresponding word line is selected, and each including a transistor element having a gate electrode extending in a same direction as the gate electrode of said drive transistor.

12. A semiconductor memory device comprising:

a plurality of static memory cells arranged in rows and columns, each memory cell including an access transistor having a gate electrode coupled to a corresponding word line, and being selectively rendered conductive according to a potential on the corresponding word line;

a plurality of word lines, arranged corresponding to the respective memory cell rows, each connected to the memory cells in a corresponding row;

a plurality of word line drivers arranged corresponding to the respective word lines, for driving corresponding word lines to a selected state according to a word line select signal; and

a plurality of pull-down elements, arranged corresponding to the respective word lines, each for lowering a voltage level of a corresponding word line when the corresponding word line is selected, and each including a transistor element having a gate electrode extending in a same direction as the gate electrode of the access transistor.

13. A semiconductor memory device comprising:

a plurality of static memory cells arranged in rows and columns, each of the memory cells including an access transistor selectively rendered conductive according to a potential of a corresponding word line;

a plurality of word lines, arranged corresponding to the respective memory cell rows, each connected to the memory cells in a corresponding row;

a plurality of word line drivers arranged corresponding to the respective word lines, for driving corresponding word lines to a selected state according to a word line select signal; and

a plurality of pull-down elements, arranged corresponding to the respective word lines, each for lowering a voltage level of a corresponding word line when the corresponding word line is selected, and each being formed of a transistor element, having threshold voltage characteristics similar to those of said access transistor, and of a same conductivity type as said access transistor.

14. A semiconductor memory device comprising:

a plurality of static memory cells arranged in rows and columns, each of the memory cells including an access transistor selectively rendered conductive according to a potential of a corresponding word line, the access transistor of the memory cell being formed of an insulated gate field effect transistor;

a plurality of word lines, arranged corresponding to the respective memory cell rows, each connected to the memory cells in a corresponding row;

a plurality of word line drivers arranged corresponding to the respective word lines, for driving corresponding word lines to a selected state according to a word line select signal; and

a plurality of pull-down elements, arranged corresponding to the respective word lines, each for lowering a voltage level of a corresponding word line when the corresponding word line is selected, and each including a transistor having a ratio of a channel width to a channel length 0.5 to 5 times larger than a ratio of a channel width to a channel length of said access transistor.

15. A semiconductor memory device comprising:

a plurality of static memory cells arranged in rows and columns, each memory cell including a load transistor connected to a cell power supply node, a drive transistor connected in series to said load transistor and having a gate connected to a gate of said load transistor, and an access transistor having a gate coupled to a corresponding word line and selectively rendered conductive in response to a potential of the corresponding word line;

a plurality of word lines, arranged corresponding to the respective memory cell rows, each connected to the memory cells in a corresponding row;

a plurality of word line drivers arranged corresponding to the respective word lines, for driving corresponding word lines to a selected state according to a word line select signal; and

a plurality of pull-down elements, arranged corresponding to the respective word lines, each for lowering a voltage level of a corresponding word line when the corresponding word line is selected, and each including a transistor element of a same conductivity type as said access transistor and said drive transistor, and having a ratio of a channel width to a channel length being in a range between a ratio of a channel width to a channel length of said drive transistor and a ratio of a channel width to a channel length of said access transistor.

16. A semiconductor memory device comprising:

a plurality of static memory cells arranged in rows and columns;

a plurality of word lines, arranged corresponding to the respective memory cell rows, each connected to the memory cells in a corresponding row;

a plurality of word line drivers arranged corresponding to the respective word lines, for driving corresponding word lines to a selected state according to a word line select signal; and

a plurality of pull-down elements, arranged corresponding to the respective word lines, each for lowering a voltage level of a corresponding word line when the corresponding word line is selected, and each including a plurality of transistor elements coupled to the corresponding word lines, respectively, wherein said plurality of transistor elements are selectively set to the on state according to a control signal.

17. The semiconductor memory device according to claim 16, wherein

each memory cell includes an access transistor rendered conductive according to a voltage on a corresponding word line, and

the transistor element has a gate electrode of a same layout as said access transistor.