Multi-pair gigabit ethernet transceiver

• US 7,570,701 B2
• Filed: 12/04/2007
• Issued: 08/04/2009
• Est. Priority Date: 11/09/1998
• Status: Expired due to Fees

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Kruse, David E., Hatamian, Mehdi, Creigh, John L., Agazzi, Oscar E., Samueli, Henry, Abnous, Arthur
• Primary Examiner(s): Corrielus; Jean B
• Application Number:
  US11/999,175
• Publication Number:
  US 20080151988A1
• Time in Patent Office: 609 Days
• Field of Search: 375/229, 375/233, 375/254, 375/285, 375259-260, 375346-350, 375/224, 375/227, 375/262, 375/265, 375/286
• US Class Current: 375/285
• CPC Class Codes: G01R 31/3004 Current or voltage test
• CPC Class Codes: G01R 31/3008 Quiescent current [IDDQ] test or leakage current test
• CPC Class Codes: G01R 31/3016 Delay or race condition test, e.g. race hazard test
• CPC Class Codes: G01R 31/31715 Testing of input or output circuits; test of circuitry between the I/C pins and the functional core, e.g. testing of input or output driver, receiver, buffer
• CPC Class Codes: G01R 31/318502 Test of Combinational circuits
• CPC Class Codes: G01R 31/318552 Clock circuits details
• CPC Class Codes: G01R 31/318594 Timing aspects clock circuits G01R31/318552
• CPC Class Codes: H04B 3/23 using a replica of transmitted signal in the time domain, e.g. echo cancellers
• CPC Class Codes: H04B 3/235 combined with adaptive equaliser
• CPC Class Codes: H04B 3/32 Reducing cross-talk, e.g. by compensating
• CPC Class Codes: H04L 1/0021 in which the algorithm uses adaptive thresholds
• CPC Class Codes: H04L 1/0047 Decoding adapted to other signal detection operation in conjunction with sequence estimation or equalization H04L25/03286
• CPC Class Codes: H04L 1/0053 specially adapted for power saving
• CPC Class Codes: H04L 1/0054 Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms
• CPC Class Codes: H04L 1/0059 Convolutional codes
• CPC Class Codes: H04L 1/006 Trellis-coded modulation
• CPC Class Codes: H04L 1/242 by comparing a transmitted test signal with a locally generated replica
• CPC Class Codes: H04L 2001/0096 Channel splitting in point-to-point links
• CPC Class Codes: H04L 2025/03363 Multilevel H04L2025/03369 takes precedence
• CPC Class Codes: H04L 2025/03369 Partial response
• CPC Class Codes: H04L 2025/03477 : not time-recursive
• CPC Class Codes: H04L 2025/0349 : as a feedback filter
• CPC Class Codes: H04L 2025/03496 : as a prediction filter
• CPC Class Codes: H04L 2025/03503 : as a combination of feedback and prediction filters
• CPC Class Codes: H04L 2025/03617 : Time recursive algorithms H04L2025/03643 takes precedence
• CPC Class Codes: H04L 2025/03745 : Timing of adaptation
• CPC Class Codes: H04L 25/03038 : with a non-recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/03057 : with a recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/03146 : with a recursive structure H04L25/03127 takes precedence
• CPC Class Codes: H04L 25/03197 : methods of calculation involving metrics
• CPC Class Codes: H04L 25/03203 : Trellis search techniques
• CPC Class Codes: H04L 25/03235 : with state-reduction using feedback filtering
• CPC Class Codes: H04L 25/03267 : with decision feedback equalisers
• CPC Class Codes: H04L 25/03987 : Equalisation for sparse channels
• CPC Class Codes: H04L 25/067 : providing soft decisions, i.e. decisions together with an estimate of reliability H04L25/068 and H04L25/069 take precedence; sequence estimation techniques H04L25/03178
• CPC Class Codes: H04L 25/14 : Channel dividing arrangements , i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
• CPC Class Codes: H04L 25/4917 : using multilevel codes
• CPC Class Codes: H04L 25/497 : by correlative coding, e.g. partial response coding or echo modulation coding transmitters and receivers for partial response systems transversal equalizers at the transmitter end H04L25/03343
• CPC Class Codes: H04L 7/0062 : detection of error based on data decision error, e.g. Mueller type detection
• CPC Class Codes: H04L 7/0334 : Processing of samples having at least three levels, e.g. soft decisions

Abstract

Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter'"'"'s partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals. This phase offset is adjusted such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized.

Claims

1. An integrated circuit communication device comprising:

a multi-state decoder operable to receive a multi-state representation signal and to generate tentative decisions and a final decision based on the received multi-state representation signal;

a single-state decision feedback equalizer operable to receive at least one tentative decision from the multi-state decoder, the at least one tentative decision corresponding to a single state of the multi-state decoder, and operable to generate a single-state intersymbol interference (ISI) compensation signal based on the at least one tentative decision;

a combiner operable to combine the single-state ISI compensation signal with an input signal to produce a single-state representation signal; and

a state multiplication circuit operable to expand the single-state representation signal received from the combiner into a multi-state representation signal suitable for decoding by the multi-state decoder.

2. The integrated circuit communication device of claim 1 wherein the single-state ISI compensation signal generated by the single-state decision feedback equalizer comprises a tail component of intersymbol interference.

3. The integrated circuit communication device of claim 2 wherein the single-state decision feedback equalizer has a set of ordered coefficients and wherein the single-state decision feedback equalizer combines the at least one tentative decision with a set of high-ordered coefficients to generate the tail component of intersymbol interference.

4. The integrated circuit communication device of claim 3 wherein the single-state decision feedback equalizer provides a set of low-order coefficients to the state multiplication circuit and wherein the state multiplication circuit expands the single-state representation signal received from the single-state decision feedback equalizer into a multi-state representation signal based in part on the set of low-order coefficients.

5. The integrated circuit communication device of claim 4 wherein the state multiplication circuit comprises a convolution element operable to combine the values of the set of low-order coefficients with a set of values representing levels of a multi-level symbolic alphabet to generate a plurality of possible ISI components.

6. The integrated circuit communication device of claim 5 wherein the state multiplication circuit is operable to subtract each of the plurality of possible ISI components from the single-state representation signal to produce a plurality of possible ISI-compensated single-state representation signals.

7. The integrated circuit communication device of claim 6 wherein the state multiplication circuit is operable to select, for each state of the multi-state decoder, one of the plurality of possible ISI-compensated single-state representation signals, wherein the multi-state representation signal generated by the state multiplication circuit comprises the selected ones of the plurality of possible ISI-compensated single-state representation signals for each state of the multi-state decoder.

8. The integrated circuit communication device of claim 7 wherein the state multiplication circuit is operable to select, for each state of the multi-state decoder, one of the plurality of possible ISI-compensated single-state representation signals based on path information received from the multi-state decoder for each state of the multi-state decoder.