Digital delay element for delay mismatch cancellation in wireless polar transmitters

• US 7,570,707 B2
• Filed: 08/25/2004
• Issued: 08/04/2009
• Est. Priority Date: 08/25/2004
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Jensen, Henrik T.
• Primary Examiner(s): Payne; David C
• Assistant Examiner(s): Panwalkar; Vineeta S
• Application Number:
  US10/925,485
• Publication Number:
  US 20060045205A1
• Time in Patent Office: 1,805 Days
• Field of Search: 375295-297, 375/300, 375/302, 375/259, 375/268, 375/269, 375/271, 375/284, 375/285, 455/149, 455/127.1, 455/91, 455/114.2, 455/114.3, 330/149, 341/50, 341/52, 341/54, 341/61, 341/122, 341/123, 708/100, 708/200, 708/290, 708/300, 708/313, 708/800, 708/801, 708/845, 708/846, 708/847
• US Class Current: 375/296
• CPC Class Codes: H03C 5/00 Amplitude modulation and angle modulation produced simultaneously or at will by the same modulating signal H03C7/00 takes precedence
• CPC Class Codes: H03F 1/0211 with control of the supply voltage or current
• CPC Class Codes: H04L 27/361 Modulation using a single or unspecified number of carriers, e.g. with separate stages of phase and amplitude modulation

Abstract

A circuit and method therefor provides programmable digital delay that is produced to introduces a delay in either an envelope or a phase signal path of an RF polar transmitter in order to eliminate the delay mismatch between the two paths. For two signal paths, a faster signal may be delayed by a digital processor or a slower signal may be transmitted early so that signals in the two signal paths arrive at a specified circuit node in synchronization. Timing shift may be implemented in either the envelope signal path or the phase signal path and may be used to reduce or increase the timing of a signal path.

Claims

1. An RF transmitter, comprising:

digital processor for producing outgoing digital IF signals comprising an envelope magnitude component and a phase component wherein the envelope magnitude component is produced on an envelope signal path and wherein the phase component is produced on a phase signal path, wherein the digital processor further includes a time shift block in at least one of the envelope and phase signal paths, wherein the time shift block implements a cubic polynomial that generates a time shift based upon a plurality of sequential sampled values of the outgoing digital IF signals to one of the envelope magnitude and phase components, the time shift block including;

a derivative estimation block for producing derivative estimates of a data sequence based upon the plurality of sequential sampled values of the outgoing digital IF signals; and

a clamped cubic spline (CCS) coefficient calculation block for producing coefficient values of the cubic polynomial based on the derivative estimates and a buffered sequence of samples;

first and second digital to analog converters (DACs) on the envelope and phase signal paths coupled to receive the envelope magnitude and phase components, respectively, the first and second DACs producing outgoing analog envelope and phase components;

first and second low pass filters for producing filtered outgoing magnitude and phase components, respectively, based upon the outgoing magnitude and phase components;

translational loop for up-converting the filtered outgoing phase component from IF to RF to produce an outgoing RF phase component; and

power amplifier that produces outgoing RF based upon the outgoing RF phase component having an outgoing power level based upon the filtered outgoing magnitude component.

2. The RF transmitter of claim 1 wherein the time shift block further includes:

a time shift split block that produces an indication of a unit time shift and an indication of a fractional unit time shift; and

a signal buffer coupled to receive the plurality of sequential sampled values of the outgoing digital IF signals, the indication of a unit time shift, and a sample rate clock wherein the signal buffer produces the plurality of sequential sampled values at each sample clock.

3. The RF transmitter of claim 2 further including a clamped cubic spline (CCS) evaluation block for producing the time shifted estimate of one of the envelope magnitude and phase components based upon the derivative estimates, the coefficient values of the cubic polynomial and a specified value of an interpolation point at which an estimate of the cubic polynomial is desired and further based upon the indication of the fractional unit time shift.

4. The RF transmitter of claim 3 wherein the signal buffer comprises a plurality of delay elements sequentially coupled and a tap on an output of each delay element and further comprises a multiplexer coupled to receive the indication of the unit time shift, the multiplexer producing delay element outputs based upon the outputs on the taps and based upon a value of the indication of the unit time shift.

5. The RF transmitter of claim 4 wherein the derivative estimation block includes an anti-symmetric FIR filter with an impulse response that is based upon the delay element outputs to produce the derivate estimates.

6. A digital processor for producing outgoing digital IF signals comprising an envelope magnitude component and a phase component wherein the envelope magnitude component is produced on an envelope signal path and wherein the phase component is produced on a phase signal path, comprising:

a time shift block in at least one of the envelope and phase signal paths;

wherein the time shift block implements a cubic polynomial that generates a time shift based upon a plurality of sequential sampled values of the outgoing digital IF signals to one of the envelope magnitude and phase components, the time shift block including;

a derivative estimation block for producing derivative estimates of a data sequence based upon the plurality of sequential sampled values of the outgoing digital IF signals; and

a clamped cubic spline (CCS) coefficient calculation block for producing coefficient values of the cubic polynomial based on the derivative estimates and a buffered sequence of samples.

7. The digital processor of claim 6 wherein the time shift block further includes:

a time shift split block that produces an indication of a unit time shift and an indication of a fractional unit time shift; and

a signal buffer coupled to receive the plurality of sequential sampled values of the outgoing digital IF signals, the indication of a unit time shift, and a sample rate clock wherein the signal buffer produces the plurality of sequential sampled values at each sample clock.

8. The digital processor of claim 7 further including a CCS evaluation block for producing the time shifted estimate of one of the envelope magnitude and phase components based upon the derivative estimates, the coefficient values of the cubic polynomial and a specified value of an interpolation point at which an estimate of the cubic polynomial is desired and further based upon the indication of the fractional unit time shift.

9. The digital processor of claim 8 wherein the signal buffer comprises a plurality of delay elements sequentially coupled and a tap on an output of each delay element and further comprises a multiplexer coupled to receive the indication of the unit time shift, the multiplexer producing delay element outputs based upon the outputs on the taps and based upon a value of the indication of the unit time shift.

10. The digital processor of claim 9 wherein the derivative estimation block includes an anti-symmetric FIR filter with an impulse response that is based upon the delay element outputs to produce the derivate estimates.

11. A method of producing outgoing digital IF signals, comprising:

producing first and second path signals corresponding to the outgoing digital IF signals on first and second circuit paths, respectively;

producing an indication of a unit time shift;

receiving a first plurality of sequential sampled values of the first path signals and further receiving the indication of the unit time shift and a sample rate clock; and

producing a second plurality of sequential sampled values at each sample clock of the sample rate clock, wherein the first plurality is larger than the second plurality;

wherein the first path signals have modified signal values that are determined by solving a cubic polynomial based upon the first plurality of sequential sampled values of the first path signals.

12. The method of claim 11 further including producing an indication of a fractional unit time shift.

13. The method of claim 12 further including producing derivative estimates of a data sequence based upon the second plurality of sequential sampled values.

14. The method of claim 13 further including producing coefficient values of the cubic polynomial based on the derivative estimates and a buffered sequence of samples.

15. The method of claim 14 further including producing a time shifted estimate of one of an envelope magnitude component and a phase component based upon the derivative estimates, the coefficient values of the cubic polynomial and a specified value of (x) and further based upon the indication of the fractional unit time shift.

16. The method of claim 15 further including producing delay element outputs based upon outputs on taps and based upon the value of the indication of the unit time shift.

17. The method of claim 15 wherein the producing the derivative estimates further includes:

using an anti-symmetric FIR filter with an impulse response that is based upon the delay element outputs to produce the derivate estimates.