Read operation for semiconductor memory devices

• US 7,571,276 B2
• Filed: 10/04/2006
• Issued: 08/04/2009
• Est. Priority Date: 10/04/2005
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Tae-Gyun, Cho, Hyun-Duk
• Primary Examiner(s): Ellis; Kevin L
• Assistant Examiner(s): Farrokh; Hashem
• Application Number:
  US11/542,140
• Publication Number:
  US 20070076484A1
• Time in Patent Office: 1,035 Days
• Field of Search: 711/103, 365/185.21, 365/185.08
• US Class Current: 711/103
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits

Abstract

Disclosed is a method of performing a read operation in a NAND/RAM semiconductor memory device. The semiconductor memory device comprises a NAND flash memory device having a memory cell array and a page buffer, and a data RAM outputting data in response to a clock signal received from a host. The method comprising; sensing data stored in one page of the memory cell array in the page buffer, transferring the sensed data from the page buffer to the data RAM in multiple blocks via a corresponding number of transfer operations, and reading the transferred data from the data RAM in response to the host clock signal, wherein a read-out operation for the transferred data commences during any one of the plurality of transfer time periods.

Claims

1. A method of performing a read operation in a memory device, the memory device comprising a NAND flash memory having a memory cell array and a page buffer;

and a data RAM configured to output data in response to a clock signal received from a host, wherein the data RAM comprises a first data RAM and a second data RAM, the method comprising;

sensing data stored in one page of the memory cell array in the page buffer;

transferring the sensed data from the page buffer to the data RAM in multiple blocks via a corresponding number of transfer operations by transferring a first block of sensed data from the page buffer to the first data RAM, and afterwards, transferring a second block of sensed data from the page buffer to the second data RAM; and

reading the transferred data from the data RAM in response to the host clock signal,

wherein a read-out operation for the transferred data commences during any one of the plurality of transfer time periods.

2. The method of claim 1, wherein the read-out operation is performed at the same time as transferring the second block of sensed data.

3. The method of claim 1, further comprising:

during the transferring of the first block of sensed data, sensing data from another page of data in the memory cell array using the page buffer.

4. The method of claim 1, further comprising:

upon completing the transferring of the first block of sensed data, outputting a control signal from the memory device to the host.

5. The method of claim 4, wherein the control signal comprises a low-high transition detected by the host.

6. The method of claim 4, further comprising:

upon detecting the to the low-high transition of the control signal, the host outputs the clock signal to the memory device.

7. The method of claim 4, further comprising:

outputting the control signal having a high-low transition to the host after the read-out operation is complete.

8. The method of claim 7, wherein the host stops outputting the clock signal in response to the high-low transition of the control signal.

9. The method of claim 1, wherein during transferring of the sensed data, data from another page in the memory array is sensed by the page buffer.

10. The method of claim 9, further comprising after the read-out operation:

transferring the sensed data of another page from the page buffer to the data RAM in multiple blocks via a corresponding number of transfer operations.

11. The method of claim 1, wherein the memory device is a One NAND flash memory device.