Semiconductor memory system for flash memory
First Claim
1. A semiconductor memory system, comprising:
- a first memory chip including a plurality of non-volatile memory blocks capable of being erased at once;
a second memory chip including a plurality of non-volatile memory blocks capable of being erased at once; and
a controller for controlling the first memory chip and the second memory chip,wherein the controller includes;
an in-use memory block assigning unit for assigning a part of the memory blocks in the first memory chip as a memory block in use to/from which read/write is performed;
a reserved memory block assigning unit for assigning a part of the memory blocks in the first memory chip as a reserved memory block;
a degradation detecting unit for detecting degradation of the memory block in use in the first memory chip;
an intra-chip block switching unit for switching the memory block in use in the first memory chip whose degradation has been detected to the reserved memory block in the first memory chip as the memory block in use;
a remaining reserved memory block count judging unit for detecting a number of the reserved memory blocks unused in the first memory chip and judging whether or not the number of the reserved memory blocks unused has reached a first predetermined value;
a memory block initializing unit for starting initialization for the memory block in the second memory chip when the number of the reserved memory blocks unused in the first memory chip reaches the first predetermined value;
a memory chip switch judging unit for judging whether or not the number of the reserved memory blocks unused in the first memory chip has reached a second predetermined value; and
a memory chip switching unit for assigning the memory block in the second memory chip which has been initialized as the memory block in use in place of the first memory chip when the number of the reserved memory blocks unused in the first memory chip reaches the second predetermined value, andwherein the first predetermined value is set, based on progression speed of the degradation of the first memory chip and speed at which the memory block initializing unit performs the initialization, to such a value that the initialization for the memory block in the second memory chip is completed during a time period between when the memory block initializing unit starts the initialization and when the number of the reserved memory blocks unused in the first memory chip reaches the second predetermined value.
1 Assignment
0 Petitions
Accused Products
Abstract
Provided is a semiconductor memory system including a plurality of main memory chips and sub-memory chips as alternatives, in which each main memory chip includes a plurality of reserved memory blocks in the same chip as alternatives to an abnormal memory block. When it is detected that the number of the remaining reserved memory blocks unused as blocks to be reassigned has reached a first predetermined value in the main memory chip, the memory blocks in the sub-memory chip starts to be formatted. When the number of the remaining reserved memory blocks unused in the main memory chip reaches a second predetermined value, read/write with respect to the main memory chip is switched to the sub-memory chip, while bypassing the format process for the memory block in the sub-memory chip. Thus, in the semiconductor memory system including a main flash memory, an alternative flash memory, and a write cache memory, the capacity of a RAM for the write cache memory can be reduced.
117 Citations
10 Claims
-
1. A semiconductor memory system, comprising:
-
a first memory chip including a plurality of non-volatile memory blocks capable of being erased at once; a second memory chip including a plurality of non-volatile memory blocks capable of being erased at once; and a controller for controlling the first memory chip and the second memory chip, wherein the controller includes; an in-use memory block assigning unit for assigning a part of the memory blocks in the first memory chip as a memory block in use to/from which read/write is performed; a reserved memory block assigning unit for assigning a part of the memory blocks in the first memory chip as a reserved memory block; a degradation detecting unit for detecting degradation of the memory block in use in the first memory chip; an intra-chip block switching unit for switching the memory block in use in the first memory chip whose degradation has been detected to the reserved memory block in the first memory chip as the memory block in use; a remaining reserved memory block count judging unit for detecting a number of the reserved memory blocks unused in the first memory chip and judging whether or not the number of the reserved memory blocks unused has reached a first predetermined value; a memory block initializing unit for starting initialization for the memory block in the second memory chip when the number of the reserved memory blocks unused in the first memory chip reaches the first predetermined value; a memory chip switch judging unit for judging whether or not the number of the reserved memory blocks unused in the first memory chip has reached a second predetermined value; and a memory chip switching unit for assigning the memory block in the second memory chip which has been initialized as the memory block in use in place of the first memory chip when the number of the reserved memory blocks unused in the first memory chip reaches the second predetermined value, and wherein the first predetermined value is set, based on progression speed of the degradation of the first memory chip and speed at which the memory block initializing unit performs the initialization, to such a value that the initialization for the memory block in the second memory chip is completed during a time period between when the memory block initializing unit starts the initialization and when the number of the reserved memory blocks unused in the first memory chip reaches the second predetermined value. - View Dependent Claims (2, 3, 4, 5, 9)
-
-
6. A semiconductor memory system, comprising:
-
a first memory module including a memory chip having a plurality of non-volatile memory blocks capable of being erased at once; a first chip controller for controlling the memory chip in the first memory module; a second memory module including a memory chip having a plurality of non-volatile memory blocks capable of being erased at once; a second chip controller for controlling the memory chip in the second memory module; and a memory module controller for communicating with the first chip controller and the second chip controller to control the first memory module and the second memory module, wherein the first chip controller includes; an in-use memory block assigning unit for assigning a part of the memory blocks in the memory chip constituting the first memory module as a memory block in use to/from which read/write is performed; a reserved memory block assigning unit for assigning a part of the memory blocks in the memory chip constituting the first memory module as a reserved memory block; a degradation detecting unit for detecting degradation of the memory block in use in the first memory module; an intra-module block switching unit for assigning the reserved memory block in the first memory module as the memory block in use in place of the memory block in use in the first memory module whose degradation has been detected; a remaining reserved memory block count judging unit for detecting a number of the reserved memory blocks unused in the first memory module and judging whether or not the number of the reserved memory blocks unused has reached a first predetermined value; and a first notifying unit for notifying the memory module controller of a fact that the number of the reserved memory blocks unused in the first memory module has reached the first predetermined value, and wherein the memory module controller includes a test command unit for commanding the second chip controller in the second memory module to perform testing the memory chip, when receiving from the first notifying unit the notification that the number of the reserved memory blocks unused has reached the first predetermined value. - View Dependent Claims (7, 8, 10)
-
Specification