System and module including a memory device having a power down mode

• US 7,571,330 B2
• Filed: 05/25/2005
• Issued: 08/04/2009
• Est. Priority Date: 03/10/1998
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Bystrom, Todd W., May, Bradley A., Barth, Richard M., Tsern, Ely K., Hampel, Craig E., Ware, Frederick A., Davis, Paul G.
• Primary Examiner(s): SURYAWANSHI, SURESH
• Application Number:
  US11/137,469
• Publication Number:
  US 20050216654A1
• Time in Patent Office: 1,532 Days
• Field of Search: 713/300, 713/324, 713/323, 713/330, 711/5, 711/167, 711/170
• US Class Current: 713/300
• CPC Class Codes: G06F 1/3225 of memory devices
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/4239 with asynchronous protocol
• CPC Class Codes: G11C 11/4072 Circuits for initialization, powering up or down, clearing memory or presetting
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 2207/2227 Standby or low power modes
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A memory module comprises a memory device including a memory array to store data. An interface receives an instruction to exit a power down mode. A register stores a value representative of a period of time to elapse between exiting from the power down mode and a time at which the memory device is capable of receiving a command to access the data. A storage device stores a plurality of parameter information that pertains to the memory device. The value is based on at least a first parameter information of the plurality of parameter information.

Claims

1. A memory module comprising:

an integrated circuit memory device including;

a memory array to store data,

an interface to receive an instruction to exit a power down mode; and

a register to store a value representative of a period of time to elapse between exiting from the power down mode and a time at which the integrated circuit memory device is capable of receiving a command to access the data; and

a storage device to store a plurality of parameter information that pertains to the integrated circuit memory device, the value to be based on at least a first parameter information of the plurality of parameter information.

2. The memory module of claim 1, wherein, while in the power down mode, the integrated circuit memory device consumes less power than after exiting the power down mode.

3. The memory module of claim 1, wherein the memory array includes an array of dynamic random access memory cells, wherein the integrated circuit memory device includes a set of sense amplifiers, wherein the command is a row activate command, and wherein data corresponding to a row of the array of dynamic random access memory cells is transferred to the set of sense amplifiers in response to the row activate command.

4. The memory module of claim 3, wherein the interface of the integrated circuit memory device includes a set of pins to receive a write command after receiving the row activate command, wherein the integrated circuit memory device inputs data to be written to the row of the array of dynamic random access memory cells in response to the write command.

5. The memory module of claim 3, wherein the interface of the integrated circuit memory device includes a set of pins to receive a read command after receiving the row activate command, wherein the integrated circuit memory device outputs read data, selected from the data transferred to the set of sense amplifiers, in response to the read command.

6. The memory module of claim 1, wherein the integrated circuit memory device includes a lock loop circuit to synchronize transfers of the data, wherein the lock loop circuit senses and tracks edges of an external clock signal to synchronize the transfers of the data, wherein the lock loop circuit reaches a predetermined state when exiting the power down mode.

7. The memory module of claim 6, wherein the predetermined state is based on when the lock loop circuit acquires synchronization with the external clock signal.

8. The memory module of claim 6, wherein the predetermined state is based on when the integrated circuit memory device is ready to receive the command.

9. The memory module of claim 1, wherein the storage device is a serial presence detect device.

10. The memory module of claim 1, wherein the plurality of parameter information includes:

information that represents a time to sense a row of the integrated circuit memory device;

information that represents a time between a row access operation of the integrated circuit memory device and a column access operation of the integrated circuit memory device;

information that represents a time between a row access operation of the integrated circuit memory device and a precharge operation of the integrated circuit memory device; and

information that represents a time between a row sense operation applied to a first bank of the integrated circuit memory device and a row sense operation applied to a second bank of the integrated circuit memory device.

11. A system comprising:

an integrated circuit memory device including;

a memory array;

a register circuit to store a value representative of a period of time to elapse before the integrated circuit memory device is ready to receive a command when recovering from a power down mode, wherein the command specifies an access to the memory array;

a delay lock loop circuit to synchronize data transfers using an external clock signal, wherein the delay lock loop circuit reacquires synchronization with the external clock signal during the period of time;

a storage area to store a parameter information that pertains to the integrated circuit memory device, the value to be derived from the parameter information; and

a memory controller device, coupled to the integrated circuit memory device, the memory controller device to provide the value to the integrated circuit memory device.

12. The system of claim 11, wherein the delay lock loop circuit reaches a predetermined state when exiting the power down mode, wherein the integrated circuit memory device is ready to receive the command upon reaching the predetermined state.

13. The system of claim 12, wherein the predetermined state is based on when the delay lock loop circuit acquires synchronization with the external clock signal.

14. The system of claim 11, wherein, while in the power down mode, the integrated circuit memory device consumes less power than in a full power mode, wherein the integrated circuit memory device receives the command while in the full power mode.

15. The system of claim 11, wherein the register circuit includes:

a first register to store first information that is representative of a first period of time in which the delay lock loop circuit acquires synchronization with the external clock signal such that a first amount of functionality of the integrated circuit memory device is achieved; and

a second register to store second information that is representative of a second period of time in which the delay lock loop acquires synchronization with the external clock signal such that a second amount of functionality of the integrated circuit memory device is achieved, wherein the second amount of functionality is greater than the first amount of functionality, wherein the period of time that elapses before receiving the command is an aggregate of the first period of time and the second period of time.

16. The system of claim 15, wherein the value is derived by summing the first period of time, expressed as a first number of clock cycles of the external clock signal, with the second period of time, expressed as a second number of clock cycles of the external clock signal, wherein:

the first number of clock cycles is based on the first period of time divided by a period of the external clock signal; and

the second number of clock cycles is based on the second period of time divided by the period of the external clock signal.

17. The system of claim 16, wherein the integrated circuit memory device is in the power down mode during initialization of the integrated circuit memory device, wherein the initialization is conducted in accordance with a first clock frequency and the integrated circuit memory device is operable in accordance with a second clock frequency during memory access operations, wherein the first clock frequency is lower than the second clock frequency.

18. The system of claim 11, wherein the integrated circuit memory device further includes an interface to receive an instruction to exit the power down mode from the memory controller device.

19. The system of claim 11, wherein the storage area and the integrated circuit memory device are disposed on a memory module, wherein the storage area is a serial presence detect.

20. The system of claim 11, wherein the memory controller device receives the parameter information from the storage area, wherein the parameter information represents a timing parameter of the integrated circuit memory device in units of time, the memory controller device to convert the parameter information that represents the timing parameter from units of time to units of clock cycles of a clock signal to derive the value.

21. The system of claim 11, wherein the parameter information includes:

information that represents a time to sense a row of the integrated circuit memory device;

information that represents a time between a row access operation of the integrated circuit memory device and a column access operation of the integrated circuit memory device;

information that represents a time between a row access operation of the integrated circuit memory device and a precharge operation of the integrated circuit memory device;

information that represents a time between a row sense operation applied to a first bank of the integrated circuit memory device and a row sense operation applied to a second bank of the integrated circuit memory device; and

information that represents a time between a precharge operation applied to a first bank of the integrated circuit memory device and a precharge operation applied to a second bank of the integrated circuit memory device.

22. The system of claim 11, wherein the memory controller device is configured in accordance with the parameter information.

23. A system comprising:

a random access integrated circuit memory device having a memory array, the random access integrated circuit memory device having an interface to receive an instruction to exit a power down mode;

a storage location to store information representing a timing parameter pertaining to the random access integrated circuit memory device; and

an integrated circuit device to generate a value representative of a period of time that elapses before the random access integrated circuit memory device receives a read command once the instruction to exit the power down mode has been received, wherein the read command instructs the random access integrated circuit memory device to output data.

24. The system of claim 23, wherein the storage location is included along with the random access integrated circuit memory device on a memory module, and wherein the storage location is included in a serial presence detect.

25. The system of claim 23, wherein the random access integrated circuit memory device includes:

a clock receiver to receive an external clock signal; and

a delay lock loop circuit to synchronize data output in response to the read command, wherein the delay lock loop circuit establishes synchronization with an external clock signal during the period of time.

26. The system of claim 25, wherein the delay lock loop circuit reaches a predetermined state while exiting the power down mode, wherein the random access integrated circuit memory device is ready to receive the read command upon reaching the predetermined state, wherein the predetermined state is based on when the delay lock loop circuit establishes synchronization with the external clock signal.

27. The system of claim 25, wherein the random access integrated circuit memory device includes:

a first register to store coarse biasing information that is associated with a first period of time during which the delay lock loop circuit acquires the external clock signal such that a limited functionality of the random access integrated circuit memory device is achieved; and

a second register to store fine biasing information that is associated with a second period of time during which the delay lock loop circuit acquires the external clock signal such that a full functionality of the random access integrated circuit memory device is achieved.

28. The system of claim 27, wherein the period of time that elapses before receiving the read command is an aggregate of the first period of time and the second period of time.

29. The system of claim 23, wherein the value is selected by dividing the period of time by a period of an external clock signal to select the value in terms of clock cycles of the external clock signal.

30. The system of claim 29, wherein the value is selected and rounded to a next whole number when a fractional number of clock cycles results when dividing the period of time by the period of the external clock signal.