Selectable JTAG or trace access with data store and output

• US 7,571,364 B2
• Filed: 08/09/2006
• Issued: 08/04/2009
• Est. Priority Date: 08/09/2005
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Whetsel, Lee D.
• Primary Examiner(s): TU, CHRISTINE TRINH LE
• Application Number:
  US11/463,479
• Publication Number:
  US 20070061646A1
• Time in Patent Office: 1,091 Days
• Field of Search: None
• US Class Current: 714/726
• CPC Class Codes: G01R 31/31722 Addressing or selecting of test units, e.g. transmission protocols for selecting test units for scan test G01R31/318558
• CPC Class Codes: G01R 31/31723 Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes routing the test signal to or from the device under test G01R31/31926
• CPC Class Codes: G01R 31/31725 Timing aspects, e.g. clock distribution, skew, propagation delay for tester hardware G01R31/31937
• CPC Class Codes: G01R 31/31727 Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/318572 Input/Output interfaces
• CPC Class Codes: G06F 11/261 by simulating additional hardware, e.g. fault simulation
• CPC Class Codes: G06F 11/267 Reconfiguring circuits for testing, e.g. LSSD, partitioning
• CPC Class Codes: G06F 11/27 Built-in tests
• CPC Class Codes: G06F 11/3466 Performance evaluation by tracing or monitoring

Abstract

An addressable interface selectively enables JTAG TAP domain operations or Trace domain operations within an IC. After being enabled, the TAP receives TMS and TDI input from a single data pin. After being enabled, the Trace domain acquires data from a functioning circuit within the IC in response to a first clock and outputs the acquired data from the IC in response to a second clock. An addressable two pin interface loads and updates instructions and data to a TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation. Trace circuitry within an IC can operate autonomously to store and output functional data occurring in the IC. The store and output operations of the trace circuitry are transparent to the functional operation of the IC. An auto-addressing RAM memory stores input data at an input address generated in response to an input clock, and outputs stored data from an output address generated in response to an output clock.

Claims

1. An integrated circuit comprising:

A. a TAP domain having a TMS input and a TDI input;

B. a data pin for inputting data to the integrated circuit;

C. an address circuit for receiving an address input from the data pin, comparing the address input against an expected address, and outputting a match signal if the address input matches the expected address;

D. a control circuit responsive to the occurrence of a match signal to enable said TAP domain; and

E. serial to parallel translation circuitry for serially inputting TMS and TDI signal packets from the data pin and outputting the TMS and TDI signals in parallel to the TMS and TDI inputs of the enabled TAP domain.

2. The integrated circuit of claim 1 including a clock signal source internal to the integrated circuit for timing the data input from the data pin to the integrated circuit.

3. The integrated circuit of claim 1 including a clock signal source external of the integrated circuit for timing the data input from the data pin to the integrated circuit.

4. An integrated circuit comprising:

A. a Trace domain operable to acquire and output data;

B. a data pin for inputting data to and outputting data from the integrated circuit;

C. an address circuit for receiving an address input from the data pin, comparing the address input against an expected address, and outputting a match signal if the address input matches the expected address;

D. a first control circuit responsive to the occurrence of a match signal to output a trace domain enable signal; and

E. a second control circuit responsive to the trace domain enable signal to enable the Trace domain to acquire data, then output the acquired data on the data pin.

5. The integrated circuit of claim 4 wherein the Trace domain acquires data in response to a first clock and outputs the acquired data on the data pin in response to a second clock.

6. The integrated circuit of claim 5 wherein the second clock is from a clock signal source internal to the integrated circuit.

7. The integrated circuit of claim 5 wherein the second clock is from a clock signal source external of the integrated circuit.

8. An integrated circuit comprising:

A. a data pin for inputting data to and outputting data from the integrated circuit;

B. an address and command circuit for inputting an address and a command from the data pin;

C. an address compare circuit for comparing the address input to the address and command circuit with an internal address of the integrated circuit and outputting a match signal if the address input matches the internal address;

D. a command decode circuit for decoding the command into one of a JTAG command operation and Trace command operation; and

E. a control circuit responsive to a match signal output from the address compare circuit to enable the decoded command operation to take effect within the integrated circuit.

9. The integrated circuit of claim 8 wherein the JTAG command operation command communicates data to and from the integrated circuit on the data pin.

10. The integrated circuit of claim 8 wherein the Trace command operation command communicates data from the integrated circuit on the data pin.