Testing circuitry for programmable logic devices with selectable power supply voltages

• US 7,571,413 B1
• Filed: 06/28/2006
• Issued: 08/04/2009
• Est. Priority Date: 06/28/2006
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Ghosh Dastidar, Jayabrata, Lee, Andy L., Perisetty, Srinivas
• Primary Examiner(s): WHITMORE, STACY
• Application Number:
  US11/478,148
• Time in Patent Office: 1,133 Days
• Field of Search: 716 16- 17, 716/4, 326 37- 38, 714725-726, 714/735
• US Class Current: 716/136
• CPC Class Codes: G01R 31/318516 Test of programmable logic devices [PLDs]
• CPC Class Codes: G01R 31/318575 Power distribution; Power saving
• CPC Class Codes: H03K 19/17744 for input/output signals
• CPC Class Codes: H03K 19/17764 for reliability
• CPC Class Codes: H03K 19/17784 for supply voltage

Abstract

A programmable integrated circuit has multiple power supply voltages. Power supply voltages are distributed using power supply distribution lines. The integrated circuit has programmable power supply voltage selection switches. Each power supply voltage selection switch has its inputs connected to the power supply distribution lines and supplies a selected power supply voltage to a circuit block at its output. Test circuits are provided for testing the power supply voltage selection switches. During testing, the power supply voltage selection switches are adjusted to produce various power supply voltages at their outputs. The test circuit associated with each switch performs voltage comparisons to determine whether the switch is functioning properly. Each test circuit produces a test result based on its voltage comparison. The test results from the test circuits are provided to a scan chain, which unloads the test results from the integrated circuit to a tester for analysis.

Claims

1. A method of testing programmable power supply voltage selection switches on a programmable integrated circuit having a plurality of test circuits, each test circuit being associated with a respective one of the programmable power supply voltage selection switches, comprising:

loading a test pattern of configuration data into the programmable integrated circuit that is used in adjusting the programmable power supply voltage selection switches to produce selected voltages at their outputs; and

using the test circuits to measure the selected voltages to produce test results, wherein the programmable integrated circuit contains a plurality of power supply voltage distribution lines each having a different associated power supply voltage, each programmable power supply voltage selection switch having inputs connected respectively to the plurality of power supply voltage distribution lines and having an output, wherein each test circuit has a first input connected to one of the plurality of power supply voltage distribution lines and a second input connected to the output of its associated programmable power supply voltage selection switch, and wherein using the test circuits comprises producing the test results by using the test circuits to compare voltages on the first and second inputs.

2. The method defined in claim 1 further comprising using a scan chain of registers to capture the test results.

3. The method defined in claim 1 wherein the programmable integrated circuit comprises a plurality of circuit blocks, wherein a respective one of the selected power supply voltages is provided at the output of each programmable power supply selection switch, and wherein each circuit block receives a respective one of the selected power supply voltages from a different respective one of the programmable power supply voltage selection switches, the method further comprising using a scan chain of registers to capture the test results.

4. A programmable integrated circuit, comprising:

a plurality of circuit blocks;

a plurality of programmable power supply voltage selection switches each of which supplies a selected power supply voltage to an associated one of the circuit blocks;

a plurality of test circuits, each test circuit making performance measurements on a respective associated one of the programmable power supply voltage selection switches and producing a corresponding test result;

a plurality of registers, each register being associated with a respective one of the test circuits and receiving the test result from that test circuit; and

a plurality of power supply voltage distribution lines, each having a different associated power supply voltage, wherein each programmable power supply voltage selection switch has inputs connected respectively to the plurality of power supply voltage distribution lines and has an output to which the programmable power supply voltage selection switch connects one of its inputs to provide the selected power supply voltage, wherein each test circuit has a first input, a second input, and an output, and wherein each test circuit produces the test result at its output based on a comparison of voltages on the first and second inputs.

5. The programmable integrated circuit defined in claim 4 wherein the registers are connected to form a scan chain.

6. The programmable integrated circuit defined in claim 4 wherein each test circuit comprises:

a transistor having a first source-drain terminal that receives a power supply voltage from one of the power supply voltage distribution lines, having a gate that receives the selected power supply voltage from the power supply voltage selection switch that is associated with the test circuit, and having a second source-drain terminal that is used in providing the test result to the register associated with the test circuit.

7. The programmable integrated circuit defined in claim 4 wherein each test circuit comprises:

a first transistor having a first source-drain terminal that receives a power supply voltage from one of the power supply voltage distribution lines, having a gate that receives the selected power supply voltage from the power supply voltage selection switch that is associated with the test circuit, and having a second source-drain terminal that is connected to a node and that is used in providing the test result to the register associated with the test circuit; and

a second transistor having a source-drain terminal connected to the node.

8. The programmable integrated circuit defined in claim 4 wherein each test circuit comprises:

a first transistor having a first source-drain terminal that receives a power supply voltage from one of the power supply voltage distribution lines, having a gate that receives the selected power supply voltage from the power supply voltage selection switch that is associated with the test circuit, and having a second source-drain terminal that is connected to a node and that is used in providing the test result to the register associated with the test circuit;

a second transistor having a source-drain terminal connected to the node and having a gate; and

a level shifter having an output connected to the gate of the second transistor.

9. The programmable integrated circuit defined in claim 4 wherein each test circuit comprises:

a transistor having a first source-drain terminal that receives a power supply voltage from one of the power supply voltage distribution lines, having a gate that receives the selected power supply voltage from the power supply voltage selection switch that is associated with the test circuit, and having a second source-drain terminal that is connected to a node; and

a NAND gate having an input connected to the node and having an output, wherein the register associated with the test circuit receives the test result from the output of the NAND gate.

10. The programmable integrated circuit defined in claim 4 wherein each test circuit receives the selected power supply voltage from its associated programmable power supply voltage selection switch and produces its test result by comparing the received selected power supply voltage to one of the power supply voltages.

11. The programmable integrated circuit defined in claim 4 wherein each test circuit comprises a first transistor that makes voltage comparisons, a second transistor that is connected to the first transistor and that has a gate, a programmable memory element having an output, and a level shifter coupled between the programmable memory output and the gate of the second transistor, wherein the level shifter reduces voltages applied to the gate of the second transistor by the programmable memory element.

12. The programmable integrated circuit defined in claim 4 wherein each test circuit comprises a first transistor that makes voltage comparisons, a second transistor that is connected to the first transistor and that has a gate, a programmable memory element having an output connected to the gate of the second transistor, and a level shifter coupled between the programmable memory element output and the gate of the second transistor, wherein the level shifter reduces voltages applied to the gate of the second transistor by the programmable memory element, and wherein each test circuit receives the selected power supply voltage from its associated programmable power supply voltage selection switch and produces its test result by using the first transistor to compare the received selected power supply voltage to one of the power supply voltages.

13. The programmable integrated circuit defined in claim 4 wherein each test circuit comprises a first n-channel transistor that makes voltage comparisons, a second n-channel transistor connected in series with the first transistor, a p-channel transistor that is connected to the second n-channel transistor and that has a gate, and a programmable memory element that produces an output signal, wherein the output signal from the memory element is used in controlling the p-channel transistor.

14. The programmable integrated circuit defined in claim 4 wherein each test circuit comprises a first p-channel transistor that makes voltage comparisons, a second p-channel transistor connected in series with the first transistor, an n-channel transistor that is connected to the second p-channel transistor and that has a gate, and a programmable memory element that produces an output signal, wherein the output signal from the memory element is used in controlling the n-channel transistor.

15. A programmable integrated circuit, comprising:

a plurality of circuit blocks;

a plurality of programmable power supply voltage selection switches each of which supplies a selected power supply voltage to an associated one of the circuit blocks;

a plurality of test circuits, each test circuit making performance measurements on a respective associated one of the programmable power supply voltage selection switches and producing a corresponding test result;

a plurality of registers, each register being associated with a respective one of the test circuits and receiving the test result from that test circuit;

a plurality of power supply voltage distribution lines;

power regulator circuitry that provides a different associated power supply voltage to each of the power supply voltage distribution lines, wherein each programmable power supply voltage selection switch has inputs connected respectively to the plurality of power supply voltage distribution lines and has an output to which the programmable power supply voltage selection switch connects one of its inputs to provide the selected power supply voltage; and

a plurality of programmable interconnection paths, each of which conveys the test result from one of the test circuits to its associated register.

16. The programmable integrated circuit defined in claim 15 further comprising:

test control logic that applies a scan enable signal to the registers, wherein the registers are organized in a scan chain with which the test results from the test circuits are captured during testing of the programmable power supply voltage switches.

17. A programmable integrated circuit, comprising:

a plurality of circuit blocks;

a plurality of programmable power supply voltage selection switches each of which supplies a selected power supply voltage to an associated one of the circuit blocks;

a plurality of test circuits, each test circuit making performance measurements on a respective associated one of the programmable power supply voltage selection switches and producing a corresponding test result;

a plurality of registers, each register being associated with a respective one of the test circuits and receiving the test result from that test circuit; and

a plurality of programmable memory elements, each programmable power supply voltage selection switch being controlled by output signals from at least one of the programmable memory elements, wherein each circuit block contains metal-oxide-semiconductor transistors that are provided with the selected power supply voltage from a respective one of the programmable power supply voltage selection switches.