Process of forming an electronic device including fins and discontinuous storage elements

• US 7,572,699 B2
• Filed: 01/24/2007
• Issued: 08/11/2009
• Est. Priority Date: 01/24/2007
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Hong, Cheong Min, Li, Chi-Nan
• Primary Examiner(s): Richards; N Drew
• Assistant Examiner(s): Lee; Kyoung
• Application Number:
  US11/626,762
• Publication Number:
  US 20080173922A1
• Time in Patent Office: 930 Days
• Field of Search: 438/156, 438/245
• US Class Current: 438/257
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42332 with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7887 Programmable transistors with more than two possible different levels of programmation
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

An electronic device can include a substrate including a fin lying between a first trench and a second trench, wherein the fin is no more than approximately 90 nm wide. The electronic device can also include a first gate electrode within the first trench and adjacent to the fin, and a second gate electrode within the second trench and adjacent to the fin. The electronic device can further include discontinuous storage elements including a first set of discontinuous storage elements and a second set of discontinuous storage elements, wherein the first set of the discontinuous storage elements lies between the first gate electrode and the fin, and the second set of the discontinuous storage elements lies between the second gate electrode and the fin. Processes of forming and using the electronic device are also described.

Claims

1. A process of forming an electronic device comprising:

forming a first trench and a second trench within a substrate, wherein a portion of the substrate lies between the first trench and the second trench, and has a width of no more than approximately 90 nm;

forming discontinuous storage elements within the first trench and the second trench;

forming a first gate electrode within the first trench and a second gate electrode within the second trench;

removing a portion of the discontinuous storage elements to form a first set of discontinuous storage elements and a second set of discontinuous storage elements, wherein the first set of the discontinuous storage elements lies between the first gate electrode and the portion of the substrate, and the second set of the discontinuous storage elements lies between the second gate electrode and the portion of the substrate; and

forming a doped region within an uppermost part of the portion of the substrate that lies between the first and second trenches, wherein in a finished device, the doped region electrically floats.

2. The process of claim 1, wherein forming the first gate electrode and forming the second gate electrode comprises:

depositing a gate electrode material over the portion of the substrate and along walls and bottoms of the first trench and the second trench; and

anisotropically etching the gate electrode material to remove a portion of the gate electrode material from over the portion of the substrate.

3. The process of claim 1, wherein:

forming the discontinuous storage elements is part of forming a charge storage stack; and

forming the first gate electrode and forming the second gate electrode comprises exposing a portion of the charge storage stack.

4. The process of claim 3, wherein removing the portion of the discontinuous charge storage elements comprises etching the portion of the charge storage stack.

5. The process of claim 3, wherein removing the portion of the discontinuous charge storage elements comprises converting the portion of the discontinuous charge storage elements to an electrically insulating material.

6. The process of claim 1, further comprising doping a first portion of the substrate along a first bottom of the first trench and doping a second portion of the substrate along a second bottom of the second trench.

15. The process of claim 2, wherein forming the first gate electrode and forming the second gate electrode is performed such that:

the first gate electrode has a first upper surface that lies at a first elevation not significantly higher than a primary surface of the substrate; and

the second gate electrode has a second upper surface that lies at a second elevation not significantly higher than the primary surface of the substrate.

16. The process of claim 2, wherein forming the first gate electrode and forming the second gate electrode is performed such that each of the first gate electrode and the second gate electrode includes a control/select gate electrode.

17. The process of claim 1, wherein removing the portion of the discontinuous storage elements is performed such That substantially all discontinuous storage elements lie within trenches, including the first trench and the second trench, within the substrate.

18. The process of claim 2, wherein:

forming the first and second trenches within the substrate is performed such that the portion of the substrate lying between the first and second trenches includes a fin; and

removing the portion of the discontinuous storage elements is performed such that a first set of the discontinuous storage elements lies between the first gate electrode and the fin, a second set of the discontinuous storage elements lies between the second gate electrode and the fin, and substantially no discontinue storage elements overlie the fin.

19. The process of claim 18, wherein removing the portion of the discontinuous storage elements is performed such that:

the first set of the discontinuous storage elements also underlies a first base of the first gate electrode; and

the second set of the discontinuous storage elements also underlies a second base of the second gate electrode.

20. The process of claim 1, wherein the portion of the substrate lying between the first trench and the second trench includes a fin having a width in a range of approximately 10 nm to approximately 50 nm.

7. A process of forming an electronic device comprising:

forming a first trench and a second trench within a substrate, wherein a portion of the substrate lies between the first trench and the second trench, and has a width of no more than approximately 90 nm;

forming discontinuous storage elements within the first trench and the second trench;

forming a first gate electrode within the first trench and a second gate electrode within the second trench;

removing a portion of the discontinuous storage elements to form a first set of discontinuous storage elements and a second set of discontinuous storage elements, wherein the first set of the discontinuous storage elements lies between the first gate electrode and the portion of the substrate, and the second set of the discontinuous storage elements lies between the second gate electrode and the portion of the substrate;

doping a first portion of the substrate along a first bottom of the first trench and doping a second portion of the substrate along a second bottom of the second trench; and

forming a third gate electrode over the fin, wherein the third gate electrode is oriented substantially perpendicular the first gate electrode and the second gate electrode.

8. A process of using an electronic device comprising:

providing a memory cell including;

a substrate, wherein a first trench and a second trench extend therein and are spaced apart from each other by a portion of the substrate;

a first gate electrode within the first trench;

a first source/drain region lying along a first bottom of the first trench, wherein the first source/drain region is coupled to a first bit line;

a second gate electrode within the second trench;

a second source/drain region lying along a second bottom of the second trench, wherein the first source/drain region is coupled to a second bit line; and

discontinuous storage elements including a first set of discontinuous storage elements and a second set of discontinuous storage elements, wherein the first set of the discontinuous storage elements lies between the first gate electrode and a first bottom of the first trench, and the second set of the discontinuous storage elements lies between the second gate electrode and a second bottom of the second trench; and

programming a first bit of the memory cell comprising;

biasing the first bit line and the second bit line at a first voltage difference;

biasing the first gate electrode, such that a second voltage difference between the first gate electrode and the first bit line is no greater than approximately half of the first voltage difference; and

biasing the second gate electrode, such that a third voltage difference between the second gate electrode and the first bit line is in a range of approximately 0.5 to approximately 1.5 times the first voltage difference, wherein a substantial fraction of current flows underneath the portion of the substrate during programming the first bit.

9. The process of claim 8, further comprising programming a second bit of the memory cell comprising:

biasing the first bit line and the second bit line at a fourth voltage difference;

biasing the first gate electrode, such that a fifth voltage difference between the first gate electrode and the second bit line is in a range of approximately 0.5 to approximately 1.5 times the first voltage difference; and

biasing the second gate electrode, such that a sixth voltage difference between the second gate electrode and the second bit line is in a range of approximately 0.5 to approximately 1.5 times the first voltage difference.

10. The process of claim 8, further comprising erasing the memory cell comprising:

biasing the substrate and the second gate electrode at a fourth voltage difference, such that the fourth voltage difference has an opposite polarity compared to first voltage difference, and the fourth voltage difference has a magnitude that is at least approximately 4 times a magnitude of the first voltage difference; and

electrically floating the first bit line and the second bit line.

11. The process of claim 8, wherein providing the memory cell comprises providing the memory cell further comprising a fin lying between the first and second trenches.

12. The process of claim 11, wherein providing the memory cell comprises providing the memory cell further comprising a doped region lying along an uppermost surface of a fin, wherein the doped region is spaced apart from the first and second source/drain regions.

13. The process of claim 12, wherein providing the doped region has a dopant concentration of at least approximately 1E19 atoms/cm³.

14. The process of claim 12, wherein programming the first bit of the memory cell is performed while the doped region electrically floats.