Programmable logic based latches and shift registers
First Claim
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1. A shift register, comprising:
- a first latch having a data input within a first logic block (LB), the first LB having a first logic element (LE) comprising an input and an output;
a second latch having a data input;
a first programmable interconnect configured to couple the first latch output to the first LE input;
a second programmable interconnect configured to couple the first LE output to second latch data input; and
a third programmable interconnect configured to decouple the first LE output to the first latch data input.
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Abstract
Disclosed is a programmable logic device adapted to implement a shift register, the device comprising: a logic block comprised of: a latch having an input; and a logic element having an output capable of coupling to an adjacent logic block and the latch input, wherein the output is coupled to the adjacent logic block and decoupled from the latch input; and an interconnect coupled to the latch and adapted to transmit the latch output to an input of the logic element. In the device, the logic element is configured as a route through for the latch output to couple to the adjacent logic block.
92 Citations
20 Claims
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1. A shift register, comprising:
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a first latch having a data input within a first logic block (LB), the first LB having a first logic element (LE) comprising an input and an output; a second latch having a data input; a first programmable interconnect configured to couple the first latch output to the first LE input; a second programmable interconnect configured to couple the first LE output to second latch data input; and a third programmable interconnect configured to decouple the first LE output to the first latch data input. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method for providing a shift register, comprising:
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providing a first latch within a first logic block (LB), the latch having an input; providing a second latch having an input; providing a logic element (LE) within the first LB, the LE having an input and an output, the LE output capable of coupling to the first and second latch inputs; coupling the first latch output to the LE input; coupling the LE output to the second latch input; and decoupling the LE output to the first latch input. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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19. A programmable logic device adapted to implement a shift register, the device comprising:
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a logic block comprising; a latch having an input; a logic element having an output capable of coupling to an adjacent logic block and the latch input, wherein the output is coupled to the adjacent logic block and decoupled from the latch input; and an interconnect coupled to the latch and adapted to transmit the latch output to an input of the logic element. - View Dependent Claims (20)
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Specification