Configurable IC with configurable routing resources that have asymmetric input and/or outputs

• US 7,573,296 B2
• Filed: 03/15/2005
• Issued: 08/11/2009
• Est. Priority Date: 11/08/2004
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Tabula Incorporated
• Inventors: Schmit, Herman, Teig, Steven, Hutchings, Brad, Huang, Randy Renfu, Redgrave, Jason
• Primary Examiner(s): Tan, Vibol
• Assistant Examiner(s): WHITE, DYLAN C
• Application Number:
  US11/082,225
• Publication Number:
  US 20070244961A1
• Time in Patent Office: 1,610 Days
• Field of Search: 326 37- 41, 326/47, 716/16
• US Class Current: 326/41
• CPC Class Codes: G06F 2207/3868 Bypass control, i.e. possibility to transfer an operand unchanged to the output
• CPC Class Codes: G06F 7/506 with simultaneous carry generation for, or propagation over, two or more stages
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA

Abstract

Some embodiments provide a configurable IC that includes several configurable tiles. The configurable tiles include several interior tiles within the interior of an arrangement of configurable tiles. The arrangement has several sides that define the exterior boundary of the arrangement. Each configurable interior tile includes a set of configurable logic circuits and a set of configurable routing interconnect circuits for routing signals between the configurable logic circuits. The set of configurable routing interconnect circuits in each interior tile has a set of inputs that are supplied by a set of asymmetric locations in the configurable IC. Any distance between any routing circuit in any interior tile and any boundary-defining side of the tile arrangement is greater than any distance between any particular routing circuit in any interior tile and any circuit that provides an input of the particular routing circuit.

Claims

1. A configurable IC comprising:

a) a plurality of configurable tiles, said configurable tiles comprising a plurality of interior tiles within the interior of an arrangement of configurable tiles, said arrangement comprising a plurality of sides that define the exterior boundary of the arrangement;

b) each configurable interior tile comprising a set of configurable logic circuits and a set of configurable routing interconnect circuits for routing signals between the configurable logic circuits;

c) the set of configurable routing interconnect circuits in each interior tile comprising a set of inputs that are supplied by a set of asymmetric locations in the configurable IC; and

d) any distance between any routing circuit in any interior tile and any boundary-defining side of the tile arrangement is greater than any distance between any particular routing circuit in any interior tile and any circuit that provides an input of the particular routing circuit.

2. The configurable IC of claim 1, wherein a set of asymmetric locations is a set of locations that comprises at least one location that has no symmetrical relationship with any other location in the set.

3. The configurable IC of claim 1, wherein the routing interconnect circuits have inputs and outputs, and a plurality of routing interconnect circuits supply their outputs as inputs to a plurality of other routing interconnect circuits.

4. The configurable IC of claim 1,

wherein the routing interconnect circuits have inputs and outputs, and the logic circuits have inputs and outputs,

wherein a plurality of routing interconnect circuits supply their outputs as inputs to a plurality of other routing interconnect circuits and to a plurality of logic circuits, and

wherein a plurality of routing interconnect circuits receive the outputs of a plurality of logic circuits.

5. The configurable IC of claim 4 further comprising a set of input-select interconnect circuits for each configurable logic circuit, wherein each particular input-select interconnect circuit for a particular logic circuit receives a set of signals for the particular logic circuit and supplies a sub-set of the received signals to the particular logic circuit.

6. The configurable IC of claim 1, wherein each configurable logic circuit is for performing a set of operations, and each particular configurable logic circuit receives a set of configuration data that controls the operation that the particular configurable logic circuit performs in the set of operations that the particular configurable logic circuit has the ability to perform.

7. The configurable IC of claim 1, wherein the plurality of configurable tiles comprises at least 300 tiles.

8. The configurable IC of claim 1, wherein the plurality of configurable tiles comprises at least 1000 tiles.

9. The configurable IC of claim 1 further comprising a plurality of configurable tiles that do not have configurable logic circuits.

10. The configurable IC of claim 1, wherein the set of configurable routing interconnect circuits in each of a plurality of tiles has a set of outputs that are supplied to a set of asymmetric locations in the configurable IC.

11. An electronic device comprising a configurable IC comprising:

a) a plurality of configurable tiles, said configurable tiles comprising a plurality of interior tiles within the interior of an arrangement of configurable tiles, said arrangement comprising a plurality of sides that define the exterior boundary of the arrangement;

b) each configurable interior tile comprising a set of configurable logic circuits and a set of configurable routing interconnect circuits for routing signals between the configurable logic circuits;

c) the set of configurable routing interconnect circuits in each interior tile comprising a set of inputs that are supplied by a set of asymmetric locations in the configurable IC; and

d) any distance between any routing circuit in any interior tile and any boundary-defining side of the tile arrangement is greater than any distance between any particular routing circuit in any interior tile and any circuit that provides an input of the particular routing circuit.

12. The electronic device of claim 11, wherein a set of asymmetric locations is a set of locations that comprises at least one location that has no symmetrical relationship with any other location in the set.

13. The electronic device of claim 11, wherein the routing interconnect circuits have inputs and outputs, and a plurality of routing interconnect circuits supply their outputs as inputs to a plurality of other routing interconnect circuits.

14. The electronic device of claim 11,

wherein the routing interconnect circuits have inputs and outputs, and the logic circuits have inputs and outputs,

wherein a plurality of routing interconnect circuits supply their outputs as inputs to a plurality of other routing interconnect circuits and to a plurality of logic circuits, and

wherein a plurality of routing interconnect circuits receive the outputs of a plurality of logic circuits.

15. The electronic device of claim 14, wherein the IC further comprises a set of input-select interconnect circuits for each configurable logic circuit, wherein each particular input-select interconnect circuit for a particular logic circuit receives a set of signals for the particular logic circuit and supplies a sub-set of the received signals to the particular logic circuit.

16. The electronic device of claim 11, wherein each configurable logic circuit is for performing a set of operations, and each particular configurable logic circuit receives a set of configuration data that controls the operation that the particular configurable logic circuit performs in the set of operations that the particular configurable logic circuit has the ability to perform.

17. The electronic device of claim 11, wherein the plurality of configurable tiles comprises at least 300 tiles.

18. The electronic device of claim 11, wherein the plurality of configurable tiles comprises at least 1000 tiles.

19. The electronic device of claim 11, wherein the IC further comprises a plurality of configurable tiles that do not have configurable logic circuits.

20. The electronic device of claim 11, wherein the set of configurable routing interconnect circuits in each of a plurality of tiles has a set of outputs that are supplied to a set of asymmetric locations in the configurable IC.