Multi-bit per stage pipelined analog to digital converters

• US 7,573,417 B2
• Filed: 02/05/2008
• Issued: 08/11/2009
• Est. Priority Date: 11/20/2007
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Agere Systems Incorporated (Broadcom, Inc.)
• Inventors: Bailey, James A., Chen, Mingdeng
• Primary Examiner(s): YOUNG, BRIAN K
• Application Number:
  US12/025,914
• Publication Number:
  US 20090128389A1
• Time in Patent Office: 553 Days
• Field of Search: 341/155, 341/156, 341/161, 341/159
• US Class Current: 341/161
• CPC Class Codes: H03M 1/167 all stages comprising simultaneous converters H03M1/165 takes precedence

Abstract

Various embodiments of the present invention provide systems and circuits that provide for conversion of analog signals to digital signals. For example, various embodiments of the present invention provide pipelined analog to digital converters. Such converters include a sub-converter and a residue amplifier. The sub-converter receives an analog input, and provides a digital representation of the analog input including a number of bits. A gain of the residue amplifier is controlled by selectably setting a group of switches. Each of the number of bits output from the sub-converter electrically controls a respective one of the switches.

Claims

1. A pipelined analog to digital converter, wherein the pipelined analog to digital converter comprises:

an analog to digital converter stage, wherein the analog to digital converter stage includes;

a multi-bit analog to digital converter, wherein the multi-bit analog to digital converter includes a particular number of comparators; and

a digital to analog converter, wherein the digital to analog converter is controlled by outputs from the particular number of comparators, wherein the digital to analog converter includes a residue amplifier with a feedback capacitance and an input capacitance, and wherein the input capacitance includes the particular number of input capacitors; and

wherein the resolution of the analog to digital converter stage is selected to reduce the number of capacitor units.

2. The pipelined analog to digital converter of claim 1, wherein each of the particular number of input capacitors is switchably coupled to a positive reference voltage or a negative reference voltage via respective switches.

3. The pipelined analog to digital converter of claim 2, wherein each of the switches is controlled by an output of a respective one of the comparators.

4. The pipelined analog to digital converter of claim 3, wherein the gain of the residue amplifier is a power of two.

5. The pipelined analog to digital converter of claim 4, wherein the particular number of comparators is four, and wherein the gain of the residue amplifier is four.

6. The pipelined analog to digital converter of claim 1, wherein the particular number of comparators is four.

7. The pipelined analog to digital converter of claim 1, wherein the digital to analog converter includes a residue amplifier with a gain of four.

8. The pipelined analog to digital converter of claim 1, wherein the analog to digital converter stage is a first analog to digital converter stage, wherein the multi-bit analog to digital converter is a first multi-bit analog to digital converter, wherein the particular number is a first particular number, wherein the digital to analog converter is a first digital to analog converter, and wherein the analog to digital converter further comprises:

a second analog to digital converter stage, wherein an input of the second analog to digital converter stage is an output of the first analog to digital converter stage, and wherein the second analog to digital converter stage includes;

a second multi-bit analog to digital converter, wherein the second multi-bit analog to digital converter includes a second particular number of comparators; and

a second digital to analog converter, wherein the second digital to analog converter is directly controlled by outputs from the second particular number of comparators.

9. The pipelined analog to digital converter of claim 8, wherein the first particular number and the second particular number are equivalent.

20. The pipelined analog to digital converter of claim 1, wherein an overall capacitance of the number of capacitor units is the same as the overall capacitance of the combination of the feedback capacitance and the input capacitance.

10. A pipelined analog to digital converter, wherein the pipelined analog to digital converter comprises:

a first analog to digital converter stage, wherein the first analog to digital converter stage provides a first multi-bit digital output and a first analog residue, and wherein the first analog to digital converter stage includes;

a first multi-bit analog to digital converter, wherein the first multi-bit analog to digital converter includes a first particular number of comparators, and drives the first multi-bit digital output; and

a first digital to analog converter, wherein the first digital to analog converter is directly controlled by outputs from the first particular number of comparators, wherein the first digital to analog converter includes a residue amplifier with a feedback capacitance and an input capacitance, and wherein the input capacitance includes the particular number of input capacitors; and

wherein the resolution of the first analog to digital converter stage is selected to reduce the number of capacitor units;

a second analog to digital converter stage, wherein the second analog to digital converter stage provides a second multi-bit digital output and a second analog residue, wherein an input of the second analog to digital converter stage is driven by the first analog residue, and wherein the second analog to digital converter stage includes;

a second multi-bit analog to digital converter, wherein the second multi-bit analog to digital converter includes a second particular number of comparators, and drives the second multi-bit digital output; and

a second digital to analog converter, wherein the second digital to analog converter is directly controlled by outputs from the second particular number of comparators.

11. The pipelined analog to digital converter of claim 10, wherein the first particular number is different from the second particular number.

12. The pipelined analog to digital converter of claim 10, wherein the first particular number is four and the second particular number is four.

13. The pipelined analog to digital converter of claim 10, wherein the first digital to analog converter comprises:

a residue amplifier with a feedback capacitance and an input capacitance, and wherein the input capacitance includes the first particular number of input capacitors.

14. The pipelined analog to digital converter of claim 13, wherein each of the first particular number of input capacitors is switchably coupled to a positive reference voltage or a negative reference voltage via respective switches.

15. The pipelined analog to digital converter of claim 14, wherein each of the switches is controlled by an output of a respective one of the first particular number of comparators.

16. The pipelined analog to digital converter of claim 15, wherein the gain of the first residue amplifier is a power of two.

17. An electronic device, wherein the electronic device comprises:

an analog signal;

a digital signal;

a pipelined analog to digital converter, wherein the pipelined analog to digital converter receives the analog signal and provides the digital signal, and wherein the pipelined analog to digital converter comprises;

a first analog to digital converter stage, wherein the first analog to digital converter stage provides a first multi-bit digital output and a first analog residue, wherein an input of the first analog to digital converter stage is driven by the analog signal, and wherein the first analog to digital converter stage includes;

a first multi-bit analog to digital converter, wherein the first multi-bit analog to digital converter includes a first particular number of comparators, and drives the first multi-bit digital output; and

a first digital to analog converter, wherein the first digital to analog converter is directly controlled by outputs from the first particular number of comparators, wherein the first digital to analog converter includes a residue amplifier with a feedback capacitance and an input capacitance, and wherein the input capacitance includes the particular number of input capacitors; and

wherein the resolution of the first analog to digital converter stage is selected to reduce the number of capacitor units;

a second analog to digital converter stage, wherein the second analog to digital converter stage provides a second multi-bit digital output and a second analog residue, wherein an input of the second analog to digital converter stage is driven by the first analog residue, and wherein the second analog to digital converter stage includes;

a second multi-bit analog to digital converter, wherein the second multi-bit analog to digital converter includes a second particular number of comparators, and drives the second multi-bit digital output; and

a second digital to analog converter, wherein the second digital to analog converter is directly controlled by outputs from the second particular number of comparators; and

wherein the digital output is a combination of the first multi-bit digital output and the second multi-bit digital output.

18. The electronic device of claim 17, wherein the first particular number is the same as the second particular number.

19. The electronic device of claim 17, wherein the electronic device is selected from a group consisting of:

a cellular telephone, a satellite receiver, a hard disk drive, and a digital radio.