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NAND flash memory cell programming

  • US 7,573,752 B2
  • Filed: 08/11/2008
  • Issued: 08/11/2009
  • Est. Priority Date: 08/04/2005
  • Status: Active Grant
First Claim
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1. A method of protecting data integrity in a non-volatile memory cell, comprising:

  • transferring a first voltage to a word line conductor at a level sufficient to reduce a snap-back condition;

    placing an intermediate voltage on a global word line conductor for coupling to the word line conductor;

    placing a second voltage on a bit line conductor if a driver signal exceeds the second voltage by at least a threshold voltage and the second voltage exceeds the intermediate voltage on the global word line conductor; and

    coupling the word line conductor to a gate of a non-volatile memory cell.

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