Global positioning system receiver and correlating circuit thereof

• US 7,574,301 B2
• Filed: 08/11/2006
• Issued: 08/11/2009
• Est. Priority Date: 11/05/2003
• Status: Active Grant

• Current Assignee: MediaTek, Inc.
• Original Assignee: Prolific Technology Inc.
• Inventors: Hsu, Chia-Chang
• Primary Examiner(s): To; Tuan C
• Application Number:
  US11/464,117
• Publication Number:
  US 20060287823A1
• Time in Patent Office: 1,096 Days
• Field of Search: 375/210, 342/357
• US Class Current: 701/213
• CPC Class Codes: G01S 19/29 carrier including Doppler, related G01S19/246 takes precedence
• CPC Class Codes: G01S 19/30 code related G01S19/246 takes precedence

Abstract

A global positioning System receiver and a correlating circuit thereof are disclosed. They sequentially and in parallel generate the portion of bits of the C/A code representing the satellite, sequentially and in parallel generate the portion of bits of the corrected frequency code of Doppler effect, and sequentially outputs the portion of bits of the C/A code and the corrected frequency code therefrom for multiplying the data and the IF data and for adding the multiplications therefrom for generating the total addition values.

Claims

1. A Global Positioning System (GPS) receiver, comprising:

a RF front end, configured to receive, demodulate and sample a RF signal for generating a IF data;

a data receiving register, coupled to the RF front end, configured to store the IF data therefrom;

a correlating circuit, coupled to the data receiving register, configured to receive the IF data for sequentially and in parallel generating a portion of bits of a C/A code representing a satellite and a portion of bits of a corrected frequency code of Doppler effect, then sequentially multiplying the portion of bits of the C/A code, the portion of bits of the corrected frequency code, and the IF data, and including a digital addition and peak detector for adding multiplications therefrom for generating a total addition value and searching a maximum thereof for identifying the satellite transmitting the IF data, wherein the digital addition and peak detector includes;

a digital adder, configured to add the multiplications therefrom for generating an I addition and a Q addition;

a square and radical calculator, coupled to the digital adder, configured to receive the I and Q additions and generating a square, addition and radical value thereof;

an integrator, coupled to the square and radical calculator, configured to integrate an output therefrom during a period of time; and

a peak detector, coupled to the integrator, configured to search a maximum of the I and Q additions for identifying the satellite transmitting the IF data;

a data extractor, coupled to the correlating circuit, configured to extract a navigation data from the IF data; and

a navigation processor, coupled to the data extractor, configured to receive the navigation data for generating a longitude-latitude data and a standard time data.

2. The GPS receiver of claim 1, wherein the correlating circuit comprises:

a parallel C/A code generating unit, sequentially and in parallel generating the portion of bits of the C/A code representing the satellite and sequentially outputting the portion of bits of the C/A code therefrom;

a parallel Doppler generating unit sequentially and in parallel generating the portion of bits of the corrected frequency code of Doppler effect and sequentially outputting the portion of bits of the corrected frequency code therefrom;

a multiplication unit, coupled to the C/A code generating unit and the Doppler generating unit, sequentially multiplying the portion of bits of the C/A code from the parallel C/A code generating unit, the portion of bits of the corrected frequency code from the parallel Doppler generating unit, and the IF data; and

the digital addition and peak detector, coupled to the multiplication unit.

3. The GPS receiver of claim 2, wherein the parallel C/A code generating unit comprises a C/A code phase loop controller adapted to sequentially output the portion of bits of the C/A code.

4. The GPS receiver of claim 2, wherein the parallel Doppler generating unit comprises a Doppler frequency loop controller adapted to sequentially output the portion of bits of the corrected frequency code.

5. The GPS receiver of claim 1, wherein the period of time is adjustable.

6. The GPS receiver of claim 2, wherein the multiplication unit can multiply 31, 32, 33, 62, 64, 66, 128 or more bits each time.

7. The GPS receiver of claim 1, wherein the data receiving register can store the IF data for about 2 ms to 20 ms.

8. The GPS receiver of claim 1, further comprises N correlating circuits, which have a structure similar to that of the correlating circuit.

9. The GPS receiver of claim 8, wherein N is 8, 10, 12 or more.