Digital signal processor having inverse discrete cosine transform engine for video decoding and partitioned distributed arithmetic multiply/accumulate unit therefor
First Claim
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1. A distributed arithmetic multiply/accumulate (MAC) unit for computing inverse discrete cosine transformations, comprising:
- a first pipeline stage of said distributed arithmetic MAC configured to perform dot products on received sequential input data, wherein row transformations are performed initially and column transformations are performed subsequent to said row transformations; and
a second pipeline stage of said distributed arithmetic MAC coupled to said first pipeline stage and configured to compute additions and subtractions of said dot products to yield sequential output data,wherein said distributed arithmetic MAC unit has a 12-bit precision.
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Abstract
A distributed arithmetic multiply/accumulate (MAC) unit for computing inverse discrete cosine transformations (IDCTs). In one embodiment, the distributed arithmetic MAC unit includes: (1) a first pipeline stage configured to perform dot products on received sequential input data and (2) a second pipeline stage coupled to the first pipeline stage and configured to compute additions and subtractions of the dot products to yield sequential output data.
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Citations
16 Claims
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1. A distributed arithmetic multiply/accumulate (MAC) unit for computing inverse discrete cosine transformations, comprising:
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a first pipeline stage of said distributed arithmetic MAC configured to perform dot products on received sequential input data, wherein row transformations are performed initially and column transformations are performed subsequent to said row transformations; and a second pipeline stage of said distributed arithmetic MAC coupled to said first pipeline stage and configured to compute additions and subtractions of said dot products to yield sequential output data, wherein said distributed arithmetic MAC unit has a 12-bit precision. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A digital signal processor (DSP), comprising:
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a core containing a pipeline control unit having a co-processor interface; and a co-processor coupled to said core and containing an distributed arithmetic multiply/accumulate (MAC) unit for computing inverse discrete cosine transformations, including; a first pipeline stage of said distributed arithmetic MAC configured to perform dot products based on sequential input data received from said co-processor interface, wherein row transformations are performed initially and column transformations are performed subsequent to said row transformations, and a second pipeline stage of said distributed arithmetic MAC coupled to said first pipeline stage and configured to compute additions and subtractions of said dot products to yield sequential output data for transmission toward said co-processor interface, wherein said distributed arithmetic MAC unit has a 12-bit precision. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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Specification