Internal memory controller providing configurable access of processor clients to memory instances
First Claim
1. A network processor integrated circuit comprising:
- a plurality of processor clients internal to the network processor integrated circuit;
an internal memory having a plurality of memory instances; and
an internal memory controller for controlling access of the plurality of processor clients to the plurality of memory instances, the internal memory controller comprising a configurable switching element;
the configurable switching element being connectable between the plurality of processor clients and the plurality of memory instances and being operative to control access of particular ones of the plurality of processor clients to particular ones of the plurality of memory instances;
wherein the configurable switching element is configurable to connect any one of at least a subset of the plurality of processor clients to each of at least a subset of the plurality of memory instances,such that in a first selectable configuration of the configurable switching element, a given one of the processor clients is permitted to access a first set of memory instances comprising one or more of the plurality of memory instances, and in a second selectable configuration of the configurable switching element, the given processor client is permitted to access a second set of memory instances comprising one or more of the plurality of memory instances, the second set being different than the first set;
wherein a different set of mask bits is associated with each of a plurality of different memory instance sizes, and a different address decoder value is associated with each of the plurality of memory instances;
wherein address decoding logic applies the mask bits for a client memory instance to an incoming address from the given processor client, and compares the result to the address decoder value for the given memory instance to determine if the incoming address is directed to an address in the given memory instance.
7 Assignments
0 Petitions
Accused Products
Abstract
An internal memory controller of a network processor or other type of processor controls access of processor clients to memory instances of an internal memory of the processor. The internal memory controller includes a configurable switching element that is connectable between the clients and the memory instances, and is operative to control access of particular ones of the clients to particular ones of the memory instances. Generally, the configurable switching element is configurable to connect any one of at least a subset of the clients to each of at least a subset of the memory instances. In a first selectable configuration of the configurable switching element, a given one of the processor clients is permitted to access a first set of one or more memory instances, and in a second selectable configuration of the configurable switching element, the given processor client is permitted to access a second set of one or more memory instances, with the second set being different than the first set.
-
Citations
15 Claims
-
1. A network processor integrated circuit comprising:
-
a plurality of processor clients internal to the network processor integrated circuit; an internal memory having a plurality of memory instances; and an internal memory controller for controlling access of the plurality of processor clients to the plurality of memory instances, the internal memory controller comprising a configurable switching element; the configurable switching element being connectable between the plurality of processor clients and the plurality of memory instances and being operative to control access of particular ones of the plurality of processor clients to particular ones of the plurality of memory instances; wherein the configurable switching element is configurable to connect any one of at least a subset of the plurality of processor clients to each of at least a subset of the plurality of memory instances, such that in a first selectable configuration of the configurable switching element, a given one of the processor clients is permitted to access a first set of memory instances comprising one or more of the plurality of memory instances, and in a second selectable configuration of the configurable switching element, the given processor client is permitted to access a second set of memory instances comprising one or more of the plurality of memory instances, the second set being different than the first set; wherein a different set of mask bits is associated with each of a plurality of different memory instance sizes, and a different address decoder value is associated with each of the plurality of memory instances; wherein address decoding logic applies the mask bits for a client memory instance to an incoming address from the given processor client, and compares the result to the address decoder value for the given memory instance to determine if the incoming address is directed to an address in the given memory instance. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
-
-
15. A method for use in a network processor integrated circuit for controlling access of a plurality of processor clients internal to the network processor integrated circuit to a plurality of memory instances of an internal memory of the network processor integrated circuit, the method comprising the steps of:
-
providing within the network processor integrated circuit an internal memory controller comprising a configurable switching element; the configurable switching element being connectable between the plurality of processor clients and the plurality of memory instances and being operative to control access of particular ones of the plurality of processor clients to particular ones of the plurality of memory instances; wherein the configurable switching element is configurable to connect any one of at least a subset of the plurality of processor clients to each of at least a subset of the plurality of memory instances; and selecting one of at least a first selectable configuration and a second selectable configuration of the configurable switching element, wherein in the first selectable configuration a given one of the processor clients is permitted to access a first set of memory instances comprising one or more of the plurality of memory instances, and in the second selectable configuration the given processor client is permitted to access a second set of memory instances comprising one or more of the plurality of memory instances, the second set being different than the first set; wherein a different set of mask bits is associated with each of a plurality of different memory instance sizes, and a different address decoder value is associated with each of the plurality of memory instances; wherein address decoding logic applies the mask bits for a given memory instance to an incoming address from the given processor client, and compares the result to the address decoder value for the given memory instance to determine if the incoming address is directed to an address in the given memory instance.
-
Specification