Bridge design for SD and MMC multiplexing

• US 7,574,549 B2
• Filed: 01/11/2008
• Issued: 08/11/2009
• Est. Priority Date: 01/11/2008
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Modu Limited (Alphabet Inc.)
• Inventors: Sherman, Itay
• Primary Examiner(s): Tan, Vibol
• Application Number:
  US12/008,501
• Publication Number:
  US 20090179668A1
• Time in Patent Office: 578 Days
• Field of Search: 326 38- 41, 326/86, 326/113, 710305-306, 710/312
• US Class Current: 710/306
• CPC Class Codes: G06F 13/4291 using a clocked protocol
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

A method for determining direction of signal transmission in a bi-directional signal line, including sampling data signals at two terminals, A and B, enabling data flow from A to B when data flow from B to A is not enabled, and a logical 0 bit is sampled at A, enabling data flow from B to A when data flow from A to B is not enabled, and a logical 0 bit is sampled at B, disabling data flow from A to B when data flow from A to B is enabled and two successive logical 1 bits are sampled at A, and disabling data flow from B to A when data flow from B to A is enabled and two successive logical 1 bits are sampled at B. An electrical circuit is also described and claimed.

Claims

1. A method for determining direction of signal transmission in a bi-directional signal line, comprising:

sampling data signals at two terminals, A and B;

enabling data flow from A to B when data flow from B to A is not enabled, and a logical 0 bit is sampled at A;

enabling data flow from B to A when data flow from A to B is not enabled, and a logical 0 bit is sampled at B;

disabling data flow from A to B when data flow from A to B is enabled and two successive logical 1 bits are sampled at A; and

disabling data flow from B to A when data flow from B to A is enabled and two successive logical 1 bits are sampled at B.

2. The method of claim 1 further comprising sampling a clock subsequent to said enabling data flow from A to B, said enabling data flow from B to A, said disabling data flow from A to B, and said disabling data flow from B to A.

3. An electrical circuit with bi-directional signal transmission, comprising:

a bi-directional data bus for connecting two terminals, A and B;

a first signal sampler for sequentially sampling a signal at terminal A;

a second signal sampler for sequentially sampling a signal at terminal B;

a first level shifter for driving signals on said data bus from

A to B, which may be enabled or disabled;

a second level shifter for driving signals on said data bus from B to A, which may be enabled or disabled; and

circuitry for enabling and disabling said first and second level shifters by carrying out instructions to;

enable said first level shifter when said second level shifter is not enabled, and a logical 0 bit is sampled by said first signal sampler;

enable said second level shifter when said first level shifter is not enabled, and a logical 0 bit is sampled by said second signal sampler;

disable said first level shifter when said first level shifter is enabled and two successive logical 1 bits are sampled by said first signal sampler; and

disable said second level shifter when said second level shifter is enabled and two successive logical 1 bits are sampled by said second signal sampler.

4. The electrical circuit of claim 3 wherein said data bus is an SD data bus.

5. The electrical circuit of claim 4 wherein terminal A has the same voltage level as terminal B.

6. The electrical circuit of claim 4 wherein terminal A has a different voltage level than terminal B.

7. The electrical circuit of claim 3 wherein said data bus in an MMC data bus.

8. The electrical circuit of claim 3 further comprising a fixed directional clock data line, and wherein said circuitry samples a clock value after each instruction.

9. An electrical circuit with bi-directional signal transmission, comprising:

a bi-directional data bus for connecting a terminal, A, with two terminals, B and C;

a controller for selectively connecting terminal A with terminal B or with terminal C;

a first signal sampler for sequentially sampling a signal at terminal A;

a second signal sampler for sequentially sampling a signal at terminal B;

a third signal sampler for sequentially sampling a signal at terminal C;

a first level shifter for driving signals on said data bus from A to B, which may be enabled or disabled;

a second level shifter for driving signals on said data bus from B to A, which may be enabled or disabled;

a third level shifter for driving signals on said data bus from A to C, which may be enabled or disabled;

a fourth level shifter for driving signals on said data bus from C to A, which may be enabled or disabled; and

circuitry for enabling and disabling said first, second, third and fourth level shifters by carrying out instructions to;

enable said first level shifter when (i) said controller selects terminal B, (ii) said second level shifter is not enabled, and (iii) a logical 0 bit is sampled by said first signal sampler;

enable said second level shifter when (i) said controller selects terminal B, (ii) said first level shifter is not enabled, and (iii) a logical 0 bit is sampled by said second signal sampler;

enable said third level shifter when (i) said controller selects terminal C, (ii) said fourth level shifter is not enabled, and (iii) a logical 0 bit is sampled by said third signal sampler;

enable said fourth level shifter when (i) said controller selects terminal C, (ii) said third level shifter is not enabled, and (iii) a logical 0 bit is sampled by said fourth signal sampler;

disable said first level shifter when said first level shifter is enabled and two successive logical 1 bits are sampled by said first signal sampler;

disable said second level shifter when said second level shifter is enabled and two successive logical 1 bits are sampled by said second signal sampler;

disable said third level shifter when said third level shifter is enabled and two successive logical 1 bits are sampled by said third signal sampler; and

disable said fourth level shifter when said fourth level shifter is enabled and two successive logical 1 bits are sampled by said fourth signal sampler.

10. The electrical circuit of claim 9 wherein terminal B has the same voltage level as terminal C.

11. The electrical circuit of claim 9 wherein terminal B has a different voltage level than terminal C.