Memory system having daisy chained memory controllers

• US 7,574,555 B2
• Filed: 03/18/2005
• Issued: 08/11/2009
• Est. Priority Date: 03/18/2005
• Status: Active Grant

• Current Assignee: Emc IP Holding Company LLC (Dell Technologies Inc.)
• Original Assignee: EMC Corporation (Dell Technologies Inc.)
• Inventors: Magnuson, Brian D., Scaringella, Stephen, Campbell, Brian K., Porat, Ofer
• Primary Examiner(s): Sough; Hyung S
• Assistant Examiner(s): Cygiel; Gary W
• Application Number:
  US11/083,571
• Publication Number:
  US 20060212622A1
• Time in Patent Office: 1,607 Days
• Field of Search: 711/5
• US Class Current: 711/105
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 12/0893 Caches characterised by their organisation or structure
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G06F 2212/263 Network storage, e.g. SAN or NAS

Abstract

A memory system having a plurality of sets of memory modules. The system includes a plurality of sets of memory controllers, each one of the memory controllers being coupled to a corresponding one of the plurality of sets of memory modules. The system includes a port for providing address and read/write control signals to the memory system. The memory controllers are interconnected in a daisy chain arrangement to the port.

Claims

1. A data storage system having an interface for coupling a host computer/server to a bank of disk drives, such interface having a pair of redundant packet switching networks, each one being coupled to front end controllers, back end controllers and a cache memory, such cache memory, comprising:

a pair of bi-directional ports, each one being connected to a corresponding one of the pair of packet switching networks, each one of the ports providing address and read/write control signals to the memory system;

a plurality of sets of memory modules;

a plurality of memory controllers, each one of the memory controllers being coupled to a corresponding one of the plurality of sets of memory modules;

wherein each one of the memory controllers includes an arbiter coupled to the corresponding one of the plurality of sets of memory modules, such arbiter being coupled to the pair of bi-directional ports to determine which one of the pair of bi-directional ports is to have access to the one of the sets of memory modules coupled to such one of the arbiters; and

wherein the memory controllers are interconnected in a daisy chain arrangement to the ports, a first one of the memory controllers in the daisy chain being coupled to a first one of the pair of ports and a last one of the memory controllers in the daisy chain being coupled to a second one of the pair of ports; and

wherein a signal path for the address and read/write control signals from the first one of the pair of ports through the controllers is in a direction opposite to a signal path for the address and read/write control signals from the second one of the pair of ports through the controllers.

2. A data storage system having an interface for coupling a host computer/server to a bank of disk drives, such interface having a pair of redundant packet switching networks, each one being coupled to front end controllers, back end controllers and a cache memory, such cache memory, comprising:

a pair of bi-directional ports, each one being connected to a corresponding one of the pair of packet switching networks, each one of the ports providing address and read/write control signals to the memory system;

a plurality of sets of memory modules;

a plurality of memory controllers, each one of the memory controllers being coupled to a corresponding one of the plurality of sets of memory modules;

wherein each one of the memory controllers receives the memory address and read/write control signals, compares the address signal with addresses of one of the sets of memory modules coupled thereto, and either addresses such one of the coupled sets of memory modules when the received address corresponds to the addresses of one of the sets of memory modules coupled thereto or passes such address and read/write control signals to a successively coupled one of the plurality of memory controllers when the received address fails to correspond to the addresses of one of the sets of memory modules coupled thereto;

wherein each one of the memory controllers includes an arbiter coupled to the corresponding one of the plurality of sets of memory modules, such arbiter being coupled to the pair of bi-directional ports to determine which one of the pair of bi-directional ports is to have access to the one of the sets of memory modules coupled to such one of the arbiters;

wherein the memory controllers are interconnected in a daisy chain arrangement, a first one of the memory controllers in the daisy chain being coupled to a first one of the pair of ports and a last one of the memory controllers in the daisy chain being coupled to a second one of the pair of ports; and

wherein a signal path for the address and read/write control signals from the first one of the pair of ports through the controllers is in a direction opposite to a signal path for the address and read/write control signals from the second one of the pair of ports through the controllers.