Memory device having a power down exit register
First Claim
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1. An integrated circuit memory device comprising:
- an interface to receive an instruction to exit a power down mode;
an array of dynamic random access memory cells; and
a register to store a value representative of a period of time to elapse between exiting from the power down mode and a time at which the integrated circuit memory device is capable of receiving a command that specifies an access to the array of dynamic random access memory cells.
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Abstract
A memory device including an array of memory cells, and a register circuit to store a value representative of a period of time to elapse before the memory device is ready to receive a command when recovering from a power down mode is provided in an embodiment. The command specifies an access to the array of memory cells. A delay lock loop circuit synchronizes data transfers using an external clock signal. The delay lock loop circuit reacquires synchronization with the external clock signal during the period of time.
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Citations
41 Claims
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1. An integrated circuit memory device comprising:
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an interface to receive an instruction to exit a power down mode; an array of dynamic random access memory cells; and a register to store a value representative of a period of time to elapse between exiting from the power down mode and a time at which the integrated circuit memory device is capable of receiving a command that specifies an access to the array of dynamic random access memory cells. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. An integrated circuit memory device comprising:
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an array of memory cells; a register circuit to store a value representative of a period of time to elapse before the integrated circuit memory device is ready to receive a command when recovering from a power down mode, wherein the command specifies an access to the array of memory cells; and a delay lock loop circuit to synchronize data transfers using an external clock signal, wherein the delay lock loop circuit reacquires synchronization with the external clock signal during the period of time. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22, 23)
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24. An integrated circuit memory device comprising:
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an array of memory cells; a register circuit to store a value representative of a time at which the integrated circuit memory device is ready to receive a command when exiting from a power down mode, wherein the command specifies an access to the array of memory cells; and a delay lock loop circuit to synchronize data transfers using an external clock signal, wherein the delay lock loop circuit reaches a predetermined state during exit from the power down mode, wherein the integrated circuit memory device is ready to receive the command upon reaching the predetermined state. - View Dependent Claims (25, 26, 27, 28, 29)
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30. An integrated circuit memory device comprising:
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a clock receiver to receive an external clock signal; an interface to receive an instruction to exit a power down mode, wherein, while in the power down mode, the integrated circuit memory device consumes less power than after exiting the power down mode; a register circuit to store a value that is representative of a period of time that elapses before receiving a read command once the instruction to exit the power down mode has been received, wherein the read command instructs the integrated circuit memory device to output data; and a delay lock loop circuit to synchronize data output in response to the read command, wherein the delay lock loop circuit establishes synchronization with an external clock signal during the period of time. - View Dependent Claims (31, 32, 33, 34, 35, 36, 37, 38, 39, 40)
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41. A method of operation in an integrated circuit memory device having an array of dynamic random access memory cells, the method comprising:
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step for receiving an instruction to exit a power down mode, wherein, while in the power down mode, the integrated circuit memory device consumes less power than after exiting the power down mode; and step for storing a value representative of a period of time to elapse between exiting from the power down mode and a time at which the integrated circuit memory device is capable of receiving a command that specifies an access to the array of dynamic random access memory cells.
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Specification