Methods for enhancing capacitors having roughened features to increase charge-storage capacity

• US 7,576,380 B2
• Filed: 08/09/2006
• Issued: 08/18/2009
• Est. Priority Date: 02/27/1998
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ping, Er-Xuan, Mercaldi, Garry A., Nuttall, Michael, Chen, Shenline, Thakur, Randhir P. S.
• Primary Examiner(s): Luu; Chuong A.
• Application Number:
  US11/502,090
• Publication Number:
  US 20060275983A1
• Time in Patent Office: 1,105 Days
• Field of Search: 257/306, 257/309, 257/296, 257/300, 257/530, 257/310, 257/529, 257/311, 257/303
• US Class Current: 257/300
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: H01L 21/28568 the conductive layers comprising transition metals H01L21/28518 takes precedence
• CPC Class Codes: H01L 21/76888 By rendering at least a portion of the conductor non conductive, e.g. oxidation
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H01L 28/82 with an enlarged surface, e.g. formed by texturisation
• CPC Class Codes: H01L 28/84 being a rough surface, e.g. using hemispherical grains
• CPC Class Codes: H01L 31/119 characterised by field-effect operation, e.g. MIS type detectors
• CPC Class Codes: H10B 12/03 Making the capacitor or connections thereto
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: H10B 53/00 Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
• CPC Class Codes: H10B 53/30 characterised by the memory core region

Abstract

Structures and methods for making a semiconductor structure are discussed. The semiconductor structure includes a rough surface having protrusions formed from an undoped silicon film. If the semiconductor structure is a capacitor, the protrusions help to increase the capacitance of the capacitor. The semiconductor structure also includes a relatively smooth surface abutting the rough surface, wherein the relatively smooth surface is formed from a polycrystalline material.

Claims

1. A semiconductor device comprising:

a dielectric layer having first and second opposite sides;

a first electrode formed on the first side of the dielectric layer, the first electrode having a first conductive barrier layer adjacent the first side of the dielectric layer and a first conductive electrode layer, the first conductive barrier layer comprising at least one of titanium nitride, tungsten nitride, tungsten silicon nitride, or titanium silicon nitride or any combination thereof, the first conductive electrode layer comprising at least one of silicon germanium or polysilicon, or any combination thereof; and

a second electrode formed on the second side of the dielectric layer.

2. The semiconductor device of claim 1, wherein the barrier layer is thinner than the first conductive electrode layer.

3. The semiconductor device of claim 2, wherein the barrier layer is thinner than 600 angstroms.

4. The semiconductor device of claim 3, wherein the barrier layer has a thickness between about 10 and about 100 angstroms.

5. The semiconductor device of claim 1, wherein the first conductive electrode layer comprises a first silicon germanium layer formed on the barrier layer, and a first polysilicon layer formed on the first silicon germanium layer.

6. The semiconductor device of claim 5, wherein the second electrode comprises a second conductive barrier layer, a second silicon germanium layer formed on the second side of the dielectric layer and a second polysilicon layer formed on the second silicon germanium layer.

7. The semiconductor device of claim 5, wherein the first polysilicon layer has a thickness of less than approximately 200 angstroms.

8. The semiconductor device of claim 5, wherein the barrier layer does not form a silicide with the first silicon germanium layer.

9. The semiconductor device of claim 5, wherein the first and second electrodes form a capacitor.

10. The semiconductor device of claim 5, wherein the first and second electrodes form an antifuse.

11. The semiconductor device of claim 1, further comprising a switch having a control terminal, an access terminal, and a storage terminal wherein one of the first and second electrodes is coupled to the storage terminal and the other of the first and second electrodes is coupled to a reference terminal.

12. The semiconductor device of claim 11, wherein the switch comprises a transistor having a gate coupled to the control terminal, a first source/drain region coupled to the access terminal, and a second source/drain region coupled to the storage terminal.

13. The semiconductor device of claim 1, wherein the dielectric is one of silicon dioxide, barium strontium titanate, or tantalum pentaoxide.

14. The semiconductor device of claim 1, wherein the second electrode is formed from at least one of polysilicon or silicon germanium.

15. The semiconductor device of claim 1, wherein the first electrode is formed with a rough surface.